Hi Guys,
I would like to know, it is a good thing if I put more than 1mA in my input stage, say 3 or 4mA. I will improve the sound quality or not? Thank you! Maxpou🙂
http://www.diyaudio.com/forums/solid-state/100669-testing-stability-3.html#post2922434
I would like to know, it is a good thing if I put more than 1mA in my input stage, say 3 or 4mA. I will improve the sound quality or not? Thank you! Maxpou🙂
http://www.diyaudio.com/forums/solid-state/100669-testing-stability-3.html#post2922434
You will have to decrease R10/R11. Vgs of the J-fet will be less at higher Id. Or, you can use higher Idss J-fets that have a larger Vgs at 3-4mA.
Thank you CBS,
but know how do for increase the bias in input stage, but it is good thing? In my memory I have read it is not good to have more than 1 mA per transistor in a differential input stage, but why I do not remember. It is the same in this topology?
Maxpou
IMHO: With bipolar transistors, base current may cause problems with DC offset, and the noise will probably be worse. There aren't problems with JFETs though.
Normally more current implies more thermal noise, because of erratic current flow inside components (resistors, semiconductors, PCB traces, etc.)
According my listening tests I can say, that the ideal current value in case of typical small signal BjT's in the input stage is 3mA until 10mA (the disadvantage of lower input impedance doesn't matter in most cases). The often choosen value below 1mA provides harsh sound quality.
By jFETs it is strong dependend from the type. For the BF245 I choice mostly 1mA.
A good solution is a Sziklai-Darlington consisting of a BF245 and a 2SC1775 or a BC414C (BC550C), if a high input impedance is important.
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If the compound pair with the J-fet and BJT is used for both polarities, the current bias of each J-fet could be different, since the optimum bias current as per noise, of the N-ch and P-ch is not likely to be the same.😉
I like to use a low Gm, low noise J-fet for the input as source follower to an emitter follower BJT ~2mA, a 2SC6026 from Toshiba. Then I cascode the two with a 4091 type J-fet. I really like that little transistor and its compliment they are great small signal amplifiers.😉
I like to use a low Gm, low noise J-fet for the input as source follower to an emitter follower BJT ~2mA, a 2SC6026 from Toshiba. Then I cascode the two with a 4091 type J-fet. I really like that little transistor and its compliment they are great small signal amplifiers.😉
In case of the topology like the schema in post #20 about
http://www.diyaudio.com/forums/solid-state/157213-acurus-a200-schematic-here-2.html
and additional jFET followers you are right.
But such mirror push pull halfs provides only a benefit by measuring results, but not in listening tests.
Thus for me only one of both LTP halfs are enough.
Post1 link shows 3mA bias current and 170/74bl.
That puts the bias @ <50% of Idss. I think this is too low.
1mA is even lower.
That puts the bias @ <50% of Idss. I think this is too low.
1mA is even lower.
this fits with what I remember about good noise performance for a BJT stage fed from a low source impedance.
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