Not sure that is the correct title but there are devices that use 3 line audio serial port (names can vary), but using CS8412 as example:
SDATA - Serial Data - audio data serial output pin
FSYNC - Frame Sync, - delineates the serial data and may indicate the particular channel, left (high) or right (low)
SCK - Serial Clock -serial clock for SDATA pin
SM5813AP oversampling filter) uses these 3 signals as input and demultiplexes them to separate left and right serial data outputs (DOL and DOR) which can be fed to two separate DACs e.g. AD1862. The demultiplexing to 2 channels is somewhat unusual as most audio devices and DACs do not use that. Also this device has DG - deglitch control clock - that can clock data to the DACs on negative going edge.
Can two separate single channel DACs be driven from the audio serial port? The FSYNC is used to clock the data in and mask off the appropriate channel on the SDATA line (some logic gates are involved) so the signals look like the illustration as below, the SDATA shows left/right channels on the same line.
So the "obvious" problem is that one of the channels is received at the DACs before the other - is that going to be a problem?
The minimum frequency of FSYNC is 44.1 kHz x 2 (sample rate of CD, both channels are sampled at 44.1 kHz) but it can be higher if oversampling is used.
The speed of sound in air is 340 ms-1 so in 1/44.1 k seconds, the sound will have travelled just under 8mm in the worst case scenario, so it will "sound like" the left channel is 8 mm nearer - surely that won't be noticeable or am I missing something?
SDATA - Serial Data - audio data serial output pin
FSYNC - Frame Sync, - delineates the serial data and may indicate the particular channel, left (high) or right (low)
SCK - Serial Clock -serial clock for SDATA pin
SM5813AP oversampling filter) uses these 3 signals as input and demultiplexes them to separate left and right serial data outputs (DOL and DOR) which can be fed to two separate DACs e.g. AD1862. The demultiplexing to 2 channels is somewhat unusual as most audio devices and DACs do not use that. Also this device has DG - deglitch control clock - that can clock data to the DACs on negative going edge.
Can two separate single channel DACs be driven from the audio serial port? The FSYNC is used to clock the data in and mask off the appropriate channel on the SDATA line (some logic gates are involved) so the signals look like the illustration as below, the SDATA shows left/right channels on the same line.
So the "obvious" problem is that one of the channels is received at the DACs before the other - is that going to be a problem?
The minimum frequency of FSYNC is 44.1 kHz x 2 (sample rate of CD, both channels are sampled at 44.1 kHz) but it can be higher if oversampling is used.
The speed of sound in air is 340 ms-1 so in 1/44.1 k seconds, the sound will have travelled just under 8mm in the worst case scenario, so it will "sound like" the left channel is 8 mm nearer - surely that won't be noticeable or am I missing something?
The minimum Fs is Fs be it 32k or 192k or anything in between. It's function isn't to clock in data, it is way too slow for that. Bit clock or serial clock does that. What FSYNC, in any of its many names and guises, does is signal the samplerate, start conversion and define, but not always, left and right. The dac, be it single or not, has a serial input register that will hold the data for each of the available channels and it is only after all the registers are loaded will conversion take place. In short, all channels are converted at the same time.