Async USB Headphone DAC

Hi all,

I'm currently fleshing out a design for a USB headphone DAC. I've recently been hacking around with the XMOS USB Audio 2.0 reference board, which interfaces quite nicely (natively) with the linux kernel and ALSA drivers.

The goal of this design is bit-perfect 24/192 audio via asynchronous USB, generated through a delta-sigma DAC, and output through a low-distortion headphone amp chip. My current chip chain is the following:

USB3318 PHY <-> XMOS XS1-L1 (-> SRC4192) -> WM8740 -> TPA6120

My question is this: with the XMOS handling asynchronous packet transfer, does the added jitter attenuation of the ASRC still outweigh its sonic alterations? In other words, is the ASRC even necessary anymore? The purist in me says I should kick it to the curb before this design goes any further, but I'll admit a lower experience level than many in this forum.


~ Brad.
Hi SoNic.

ASRC is definitely an option to consider.

Correct me if i'm wrong, but given the fact that asynchronous usb allows the DAC itself to generate the master clock signal, doesn't the usefulness of an ASRC in this application reduce down to its ability to perform upsampling?

Even if you do a separate miniboard that can be interposed in the data stream...

Either that or actually adding muxes to switch the ASRC in and out of the data path and controlling them from the XMOS. The USB Audio Class 2.0 exposes a Sampling Rate Converter Unit (RU) to the host; does anyone with more experience with this spec want to say whether or not the RU can be switched in and out of the chain in this manner? I'm still trying to decipher the spec...

~ Brad.
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On second thought, even adding an ASRC into the design is a serious complication. One clock mux would be required to match the input sampling rate to the XMOS and another clock mux would be required to match the output sampling rate to the ASRC and DAC. At that point, at least in my mind, I might as well just skip the XMOS and go straight to an FPGA solution in which the asynchronous USB audio, clock muxing, data muxing and sample rate conversion are performed on the same chip...

... so to keep things simple, I'm kicking the ASRC to the curb for this run and saving the FPGA implementation for another day. ;)

I plan on posting more information as the design progresses. Please feel free to chime in and offer advice, suggestions or criticisms.

~ Brad.

P.S.: does this thread need to be moved to the Digital Line Level forum??
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... so to keep things simple, I'm kicking the ASRC to the curb for this run and saving the FPGA implementation for another day. ;)

Long time, no see :D I agree with you - a true async implementation can only have its jitter made worse by including an ASRC, so kick it out. An ASRC is only as good as what it thinks your output clock is, and that's the 'analogy' part of ASRCs which has the greatest potential for degradation (assuming that the digital bits are done by the book). It has usefulness if you want upsampling though - at the expense of it introducing some jitter which can't be subsequently corrected for.

All that being said, I'm currently listening through a CS8421 and haven't noticed any nasties yet.
Long time, no see :D

Quite true. :) Grad school, unfortunately, has a way of keeping one quite busy. Actually i'm curious now, if you had to pick a 24/192-capable DS DAC to listen to, of those you've heard, which would you choose and why? My heart isn't quite firmly set on the WM8740 yet, even if I'm leaning that direction.

~ Brad.
I'm not a believer in being able to hear a DAC chip in isolation, implementation is the main determiner of sound quality. That said, I'll always tend to veer towards current out DACs for the simple reason that I don't totally trust CMOS opamps (as found in voltage out DACs) vis-a-vis sound quality. So AD1955 or PCM179X for me it would have to be.


2003-09-03 12:17 pm
I agree that USB async makes it unnecessary to add an ASRC.

In my opinion though, it's much easier to go with a classical pcm2707-src4192 chain than to bother with async. Jitter is of no concern thanks to the src4192 (see this post by Bruno Putzeys: ) and the upsampling provided by the ASRC is nice to facilitate the analog filtering. But of course, I've never been convinced of the advantages of 24/192 over the good old 16/44.1.

PS: I'm currently very, very happy with a pcm2707-SRC4192-PCM1798-OPA1632 dac (final output stage is discrete jfet stuff). If you're using differential opamps for I/V, beware of capacitive loads and of keeping the dac outputs at 0V.
Actually, as USB audio 2.0 supports up to 32-bit samples, I don't see any reason for not using the WM8741, but the daughterboard will still use the '40, since they're pin-compatible.

Here's what I've come up with for the daughterboard to the XMOS UAC2 board. The DAC is configured for normal stereo mode 24-bit I2S without de-emphasis and without muting. ;)

~ Brad.


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