array of micro speakers with shading in ATH4 horn

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#22
The difference between them is pretty small, both look quite bad outside the narrow vertical window but that is quite normal and in the polar curves it is because only one of the measurement points is within the usable window.
 

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#25
All a bit tiny down there. Sanity check on the filter network and buffer.

I'm connecting the OUTPUT of one LME49721 to 20 parallel MAX9718A amplifers with 10k input resistors.

The LME49721 output current is 9mA max at 5V supply. Is my OUTPUT buffer arrangement sufficient?


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Input filter network
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MAX9718A amplifer
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filter network repsonse, group delay and phase
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#30
I replicated the report settings as best I could to match the ATH4 CE260 report for a A/B comparison.

I have left another batch running over night. Maybe I'll get closer still to the CE260 performance.

* I have not normalised to 10deg - will do that in the morning.

limacon_test.png

CE260.png
 
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#35
limacon said:
@fluid thanks!

I'm beginnng to think this may be a futile endeavour and eat chocolate instead.
Click to expand...
Don't get discouraged, this is the nature of arrays, they do not behave the same way as a single driver.

You might think that 5 degrees is the vertical window but it isn't, when you move up or down within the bounds of the lines ends the response vertically is exactly the same.

For example I moved the observation point 70mm higher and the vertical graph is the same. This might not seem right but it is.


Split Small Different Vertical.png
 
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#37
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#38
Today I designed a dev board for an old PWM dsp from D2 Audio / now Renesas.

https://www.renesas.com/us/en/produ...lligent-digital-amplifier-and-sound-processor

I have 12 channels of PWM high & low buffered output (SN74LVC2G34) at 5.5V. SNR>110dB & THD+N <0.01% .

  • 2 x I2S input
  • 2 x SPDIF input
  • 1 x SPDIF output
  • protection inputs
  • 90mm x 120mm

MCU for initial programming to the dsp memory plus volume & tilt pot.

In theory I could use the PWM high & low buffered outputs as speaker low output test drivers (25ma) with suitable filtering.

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#40
Sanity check using the NTTFD4D0N04HL on a tiny board ( 50mm x 19mm )

Max RDS(on) = 7mΩ at VGS = 4.5V
Rise and fall pretty good.

As this will be for "ribbon emulator" frequencies I am proposing a half bridge with single pole high pass bias network to improve PSRR.

Not sure about the comps or vals yet. I'll sleep on it.

Comments welcomed!


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