Anybody using the new ESS Vout DAC (ES9022)?

Status
Not open for further replies.
Jump to Latest
#463
As agreed with Joachim Gerhard, who kindly offered the filter buffer circuit to all DIYers, here is the arrangement.

We shall offer, in a Group Buy with minimum 25 PCBs, the PCB for the JG Filter Buffer as posted in here :

http://www.diyaudio.com/forums/digi...ng-new-ess-vout-dac-es9022-8.html#post3040691

On the PCB will be soldered a total of 8 Idss matched JFETs (4x BF862, 4x MMBFJ310).
We still need to calculate labour cost for matching and soldering.
But the entire package is likely to be around HK$350 (~44USD) including Paypal fees and registered air mail worldwide.

You will get a Bill of Material so that you can order and solder the remaining components.

This is a one time offer.
After the GB, the board is still available on request, but our normal conditions will apply.
i.e. orders under HK$500 will be subjected to a service charge.

We'll conform exact price in a few days.


Patrick
 
#476
I've noticed the general consensus around here is 45.1584MHz master clock with sync clocking.

The datasheet suggests this config will not support fs=44.1kHz in sync mode (there is no 1024 multiple in the table of sync frequencies). Will this still work, but the DAC internally will operate in async mode; or ???

Since the overwhelming majority of my media is 44.1kHz I am trying to select the optimum master-clock frequency for the media I will use most of the time ...
 
#478
Thanks Patrick, it was your recommendations that started my search for a faster masterclock. So you have confirmed that it works with fs = 44.1kHz.

I am trying to rationalise if this is an unsupported sync mode or is it actually async?

The ES9023 datasheet does not show a 1024*44.1 = 45.1584MHz frequency being in the set of freq supported for sync masterclock, in fact it shows no column at all for 1024 * fs.

I have a WaveIO XMOS usb->i2s card from lorien with 22MHz NDK XO, I am considering adding Ian's FIFO board with crystek 45MHz XO but the way I read the datasheet this won't strictly fall within the sync criteria set out in the table on page 4 of the ES9023 datasheet, perhaps I am being too pedantic?

Chris
 
#479
I think you have a point. The only one who can answer this is ESS, so why not wriite to ask them.

If there is a jitter rejection routine in the asyn mode (max 50MHz), and the incoming data happens to be in syn with MCLK,
it would be a really lousy routine that will add jitter. So I presume it is effectively in syn at 45MHz.

Anyhow the ES9022 is not my reference design.
So I do not go to the last 0.1% details with that.
And it is easy enough to just use 22MHz.
If you cannot hear a difference, then it is all that matters.

🙂


Patrick

PS I have not tried 22MHz myself.
 
Status
Not open for further replies.
Top Bottom