Amp power calculations into different phase angles

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Jan

I think SB is driven by high Vce and NOT by high temp (it is in the end but only because SB leads to local hotspots)

I agree that SB is initiated by Vce but it is relatively high temperatures which causes the run-away. Damaging the silicon requires the hotspot to reach ~1000C or more. This is what I meant by "driven by high temperature"- that is if damage occurs.

John
 
john_ellis said:
Jan



I agree that SB is initiated by Vce but it is relatively high temperatures which causes the run-away. Damaging the silicon requires the hotspot to reach ~1000C or more. This is what I meant by "driven by high temperature"- that is if damage occurs.

John


Hi John,

Agree fully. But I still have a question that is relevant to what I am trying to do.

My protection system gets two pieces of information: one is the instanteneous Ic, the other is the instantaneous Vce. Now, if the temp is increasing, I must derate the Pc/Ic meaning start the limiting at lower Ic. But should I then also start limiting at lower Vce, or can I leave that as is? Because, as we seem to agree, the onset of SB doesn't start earlier with higher temp. And as long as SB is not initiated, the higher temp doesn't matter - for SB. That's how I understood it, at least.

Jan Didden
 
janneman said:
My protection system gets two pieces of information: one is the instanteneous Ic, the other is the instantaneous Vce. Now, if the temp is increasing, I must derate the Pc/Ic meaning start the limiting at lower Ic. But should I then also start limiting at lower Vce, or can I leave that as is? Because, as we seem to agree, the onset of SB doesn't start earlier with higher temp. And as long as SB is not initiated, the higher temp doesn't matter - for SB.
Hi,
the trigger transistor obtains it's base current from the I sensor AND from the V sensor. It effectively adds these two sensor currents and this raises the base voltage towards the trigger voltage. (I guess it's a soft trigger as it starts to conduct).
Assume for a moment that Ic has stayed constant and that Vce is moving up as the waveform progresses. The sum of those two sensor currents will trigger as the Vce sensor supplies sufficient extra current for the protection transistor to start conducting.

If the output transistors have become hotter than the cold set up then you rightly want an earlier trigger voltage i.e. at a lower Vce at the fixed Ic we assumed.
This could be approximated by your heatsink coupled protection transistor (this was discussed some months ago and although probably not exactly what is required at least moves the trigger point in the right direction) Certainly my modified Bensen sheet shows quite clearly the lower protection locus as the trigger voltage is re-set to a lower value.
It matters little whether the Ic moves while Vce is fixed or if both sensor currents are changing. The protection transistor is still instananeously summing the two currents.

The adding of the two sensor currents is possibly the equivalent to mutiplying V * I since the result follows a power law for a small portion of the protection locus. It is certainly not multiplication for the highest currents (low Vce) nor for the lowest currents (high Vce) but this error in the shape of the curve is fortuitously just what we need to mimic the DC SOA at the asymtotes.

To me it seems, the much more important parameter that needs changing is short term transient trigger voltages (the RC delay) to prevent early triggering on short peaks that the output stages can easily pass and survive.
 
AndrewT said:
[snip]If the output transistors have become hotter than the cold set up then you rightly want an earlier trigger voltage i.e. at a lower Vce at the fixed Ic we assumed.[snip]


That I question! Why should we trigger earlier on a specific Vce because the transistor is hotter? I want an earlier trigger with Ic, but not Vce. IOW, the network sensing Vce and providing a related input to the protection transistor doesn't need to be temp sensitive. The network that samples Ic and provides an input does need to be temp sensitive.
(Forget for the moment that many practical implementations cannot separate the two effects, we're talking principles here).

Jan Didden
 
Hi Jan

I think what we agree on is that for higher temperatures, the protection circuit needs to trigger at a lower Ic. This automatically reduces the power allowed in the transistor. The Vce needs to be left alone, as it were, because this does not change!

In a classical protection circuit of the type Andrew suggests the base sees a signal from Vce and another from Ie which is being summed and the two form a load line which needs to be large enough to avoid being triggered by pulses/reactive load lines etc.

Maybe a simple temperature compensation would be to put the protection transistor onto the same heatsink as the output devices. As this warms, the protection load line reduces. I haven't thought this fully out as to whether the temperature compensation is sufficient. But as we also agree on the ISB limit not being as critical as the overall dissipation at higher temperatures, maybe this will be enough.

It is also quite permissible to allow the pulse power rating to be used, increasing the power output capability on a temporary basis, and a delayed turn-on in the protection can do this. But then some additional protection is needed to prevent overloads during the delay time... so I'm sure that there is scope for a comprehensive protection arrangement to be designed.

cheers
John
 
Hi John & Jan,
we are on the same wavelength.
Assume for a moment
It matters little whether the Ic moves while Vce is fixed or if both sensor currents are changing. The protection transistor is still instantaneously summing the two currents.
summed and the two form a load line
and once these are summed then
I want an earlier trigger with Ic
is achieved.
possibly the equivalent to mutiplying V * I since the result follows a power law for a small portion of the protection locus
confirms we are de-rating power at least on part of the protection locus.

There was an extended discussion on mounting the protection transistor on the sink and whether it came close to compensating correctly or at all.
The consensus was that the temperature compensation was not accurate but that it undercompensated. It was also agreed that linking sink to prot Q did move the protection locus in the correct direction for operation at elevated temperatures (anything above 25degC).
RC filtering is pretty effective in providing a delay that adjusts itself inversely with signal level. That inverse property is exactly what the semiconductors need.
Significant attenuation on very short lived spikes and little attenuation of near DC signals. Similarly small delay on very high signal levels and higher delay on signals that just exceed the trigger levels. I think the simple RC connected protection transistor can do the job we need, particularly if I knew how to design the RC part of it. I wish simulators were within my intellectual grasp.
 
AndrewT said:
Hi John & Jan,
we are on the same wavelength. and once these are summed then is achieved. confirms we are de-rating power at least on part of the protection locus.

There was an extended discussion on mounting the protection transistor on the sink and whether it came close to compensating correctly or at all.
The consensus was that the temperature compensation was not accurate but that it undercompensated. It was also agreed that linking sink to prot Q did move the protection locus in the correct direction for operation at elevated temperatures (anything above 25degC).
RC filtering is pretty effective in providing a delay that adjusts itself inversely with signal level. That inverse property is exactly what the semiconductors need.
Significant attenuation on very short lived spikes and little attenuation of near DC signals. Similarly small delay on very high signal levels and higher delay on signals that just exceed the trigger levels. I think the simple RC connected protection transistor can do the job we need, particularly if I knew how to design the RC part of it. I wish simulators were within my intellectual grasp.

Andrew,

You're right of course, I was just looking at it from a principle way, without concern of the way the two information pieces are summed in the "classical" way (but where's the fun in the "classical way" ehh?).

I think we beat this particular horse to death sufficiently.

Jan Didden
 
Caveat.

While fascinating, this approach is of dubious utility in practice as one is very unlikely to encounter a loudspeaker system capable of generating a 90degree impedance phase shift; this is attested to by Stereophile's impedance response graphs of hundreds of loudspeakers.

The loading presented by a full range loudspeaker system is unlikely to be worse than 4ohms at 60degrees phase shift.
 
"'would like to see your circuit nevertheless."

Jan,

Me too, and this sounded interesting (similar to mine, which has one breakpoint?):


"the spreadsheet to automagically calculate the protection circuit component values interactively by setting the breakpoints on the graph to follow any required shape with two breakpoints".


Regards,

Brian.
 
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