Hi Everyone !!!
I want to build a home brew ADAT decoder using an FPGA. I have already a working SPD/IF receiver.
Does anyone have any info on the ADAT data structure? I have read the Alesis patent 5,297,181 wich explains the basic coding but it does not reveal bit order and has nothing about how the "user bits" are implemented in commercial encoders.
Any help here is very much appreciated. 🙂
Sincerely,
Christian
I want to build a home brew ADAT decoder using an FPGA. I have already a working SPD/IF receiver.
Does anyone have any info on the ADAT data structure? I have read the Alesis patent 5,297,181 wich explains the basic coding but it does not reveal bit order and has nothing about how the "user bits" are implemented in commercial encoders.
Any help here is very much appreciated. 🙂
Sincerely,
Christian