Given the shortages of 36.864Mhz oscilators.. I’m looking at cunning options..
The normal ways of clocking on the RPI/STM are:
Software GPIO toggling (including interrupt) - slow and inefficient
DMA pin set - works but uses bus (more efficient than software) but unreliable.
Hardware PWM - maxes out in the low MHz
Timer with force - with a 480Mhz chip this maxes out at 1/2 system clock (200+Mhz) this could be configured 1:13 and you’d get a 36.864MHz clock
HDMI TDMS - configuring the right screen pixel resolution, bits/pixel and fps means you can get a 36.864MHz pixel clock on the TDMS clock pin.
Anyone tried the last two?
The normal ways of clocking on the RPI/STM are:
Software GPIO toggling (including interrupt) - slow and inefficient
DMA pin set - works but uses bus (more efficient than software) but unreliable.
Hardware PWM - maxes out in the low MHz
Timer with force - with a 480Mhz chip this maxes out at 1/2 system clock (200+Mhz) this could be configured 1:13 and you’d get a 36.864MHz clock
HDMI TDMS - configuring the right screen pixel resolution, bits/pixel and fps means you can get a 36.864MHz pixel clock on the TDMS clock pin.
Anyone tried the last two?
Both options will be troublesome The 1:13 may work with an external divider but the internal divider will most likely create some significant spurs.
The HDMI source may blip with retrace. The HDMI signals are TMDS or transition minimized differential signaling- They are self clocked with minimized transitions so you may not get what you expect. The clock signal is a division of the bit clock to keep the frequencies and the noise down. The usual commercial way to get those AV clocks are some specialized clock generator chips with low jitter pll/programmable dividers. They work pretty well. e.g. https://www.ti.com/lit/ds/symlink/l...94391&ref_url=https%3A%2F%2Fwww.google.com%2F
The HDMI source may blip with retrace. The HDMI signals are TMDS or transition minimized differential signaling- They are self clocked with minimized transitions so you may not get what you expect. The clock signal is a division of the bit clock to keep the frequencies and the noise down. The usual commercial way to get those AV clocks are some specialized clock generator chips with low jitter pll/programmable dividers. They work pretty well. e.g. https://www.ti.com/lit/ds/symlink/l...94391&ref_url=https%3A%2F%2Fwww.google.com%2F