hi, oli
Show schematic circuit diagram and I can give you some advice. Exchange the L and R channels' opa627 to see if the problem caused by OPA627.
Show schematic circuit diagram and I can give you some advice. Exchange the L and R channels' opa627 to see if the problem caused by OPA627.
A possible cure for dc offset problem?
Thanks for your interest AD1865, I will next post my IV schematic- I'll scan it tomorrow. In the mean time, here's a possibilty. Tell me what you think please...
The OPA627 is configured as a current summing (inverting) amplifier, with non-inverting input at ground potential and the inverting input connected to the DAC. feedback is achieved via the AD1865 internal feedback resistor. Pretty textbook stuff.
I have done some research and discovered that d.c. offset can arise from unbalanced input impedances. In my case...
The non-inverting input is almost 0R.
The inverting input has the equivalent parallel combination of feedback resistance (3k) and DAC output impedance (1.8) = 1.1k.
If I ground the non-inverting input through a 1.1k resistor, a similar input impedance should exist on both inputs and my d.c. offset problem will improve.
Does this sound reasonable?
Why is this method never suggested in classic IV converter schematics? ( because it introduces a little noise through the non-inverting input? )
Thanks for your interest AD1865, I will next post my IV schematic- I'll scan it tomorrow. In the mean time, here's a possibilty. Tell me what you think please...
The OPA627 is configured as a current summing (inverting) amplifier, with non-inverting input at ground potential and the inverting input connected to the DAC. feedback is achieved via the AD1865 internal feedback resistor. Pretty textbook stuff.
I have done some research and discovered that d.c. offset can arise from unbalanced input impedances. In my case...
The non-inverting input is almost 0R.
The inverting input has the equivalent parallel combination of feedback resistance (3k) and DAC output impedance (1.8) = 1.1k.
If I ground the non-inverting input through a 1.1k resistor, a similar input impedance should exist on both inputs and my d.c. offset problem will improve.
Does this sound reasonable?
Why is this method never suggested in classic IV converter schematics? ( because it introduces a little noise through the non-inverting input? )
The offset of OPA627 is very low
Use jfet input stage, OPA627 have very low input bias current, so the unbalanced impedance nearly no effect on DC offset.
You can use the OP in AD1865 to see if it also have big offset.
Use jfet input stage, OPA627 have very low input bias current, so the unbalanced impedance nearly no effect on DC offset.
You can use the OP in AD1865 to see if it also have big offset.
Ok I'll try
I have tried swapping OPA627 left and right channels- the bias still exists on original channel only.
If I understand you correctly, the balancing of input inpedance is not really a problem with fet opamps. The input current is so low that little potential diffence can arise.
I have tried swapping OPA627 left and right channels- the bias still exists on original channel only.
If I understand you correctly, the balancing of input inpedance is not really a problem with fet opamps. The input current is so low that little potential diffence can arise.
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