A NOS 192/24 DAC with the PCM1794 (and WaveIO USB input)

Official Court Jester
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at first the e-301 sounded sharper/livelier/faster/more defined than the lm334
came back an hour later and then changed my mind

ive no explanation for it
could me my mistake either

you can really compare them as apples to apples only on exactly same set current

good thing with 334 is guaranteed low working voltage ( so squeezable from pin 20 to gnd) , and having even possibility to additionally squeeze tempco correcting uni diode in series

though , even if I believe that there is no need for it
 
Which parts did you use for your JFET CCS Ross?

1. 2SK170 with an Idss of about 7ma (anything from 6-10ma should be ok)

The combination of the following two resistors measured 710 ohms to provide 0.4ma
2. 470ohm Dale RN55 1/10watt
3. 1k Bourns pot (a 500ohm pot would be a better match)

I'm listening to my fully tweaked single board DDDAC with the JFET CCS in it as I write this. If anything, I like it at least as much as the 2 transistor CCS. Maybe the signal generator break-in was more complete. Maybe reducing the Rload voltage a bit sounds better. Maybe the 2SK170 JFET is injecting some 2nd order harmonic distortion into Iref. So many variables.
 
For the LM334 the tempco is documented to be 0.33%/Celcius. Last night I measured the temperature of my DDDAC 4 board stack in its enclosure after several hours of use. The top board measured between 40C and 43C in places (at 22C ambient), which was a bit more then I expected. So, we are looking for 0.4mA, therefor it looks like a temperature swing from room temperature at say 22C to 43C will result in a current swing of 0.03mA, between these two extremes in my situation.
 
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1. 2SK170 with an Idss of about 7ma (anything from 6-10ma should be ok)

The combination of the following two resistors measured 710 ohms to provide 0.4ma
2. 470ohm Dale RN55 1/10watt
3. 1k Bourns pot (a 500ohm pot would be a better match)

I'm listening to my fully tweaked single board DDDAC with the JFET CCS in it as I write this. If anything, I like it at least as much as the 2 transistor CCS. Maybe the signal generator break-in was more complete. Maybe reducing the Rload voltage a bit sounds better. Maybe the 2SK170 JFET is injecting some 2nd order harmonic distortion into Iref. So many variables.

this all loods very promising! I am pretty busy with another project, which I will reveal later, when first prototypes are sounding good, so have been mixing things a bit recently. I will get some JFETS quickly. honestly, I think it hardly matters what JFET is being used, as long as the impedance is high.... meaning, you are looking for a low as possible source resistor, or decouple this resistor. bad thing is, that will be a large capacitor! Carlson, as you are the one having the test setup right now, could you check any impact of decoupling the source resistor?

as soon as I have a FET in my pin 20 test dac, I can report what I think on the sound and also can back up some measurement of 6k versus FET with the AP machine to see if we can find a correlation.

that 2.4 volt is stable is logical as we can see this from the internal drawings we saw in earlier posts... there is a reference voltage inside the 1794, so this will be rock solid.

only thing I still do not like is the enormous spread in Idss and hence the needed trimmer. not DIY friendly, but for the die-hard tweakers no issue of course.

if all seems worth it at the end of the day, I can pack this next to the next board design. if you than put in a stable 6k resistor or a JFET with trimmer is up to the user so to speak.
 
good question,

this will happen:

new Bias current will be 13.3 mA
new Rload need to be 100 ohm, VDC 2,66 volt

tbh i dont understand this stuff very well, in regards the output currents

the data sheet says on page 24

Analog output
The following table and Figure 31 show the relationship between the digital input code and analog output.

800000 (–FS) 000000 (BPZ) 7FFFFF (+FS)
IOUTN [mA] –2.3 –6.2 –10.1
IOUTP [mA] –10.1 –6.2 –2.3
VOUTN [V] –1.725 –4.65 –7.575
VOUTP [V] –7.575 –4.65 –1.725
VOUT [V] –2.821 0 2.821

i assumed this was for normal stereo mode and that as your design is mono and using 8v dc instead of 5v that this would change these datasheet figures substantially, maybe even doubled the output mA?

are there voltage levels on vcom or output bias that could be damaging?
 
this all loods very promising! I am pretty busy with another project, which I will reveal later, when first prototypes are sounding good, so have been mixing things a bit recently. I will get some JFETS quickly. honestly, I think it hardly matters what JFET is being used, as long as the impedance is high.... meaning, you are looking for a low as possible source resistor, or decouple this resistor. bad thing is, that will be a large capacitor!

could you explain what you mean?...

Carlson, as you are the one having the test setup right now, could you check any impact of decoupling the source resistor?

as soon as I have a FET in my pin 20 test dac, I can report what I think on the sound and also can back up some measurement of 6k versus FET with the AP machine to see if we can find a correlation.

that 2.4 volt is stable is logical as we can see this from the internal drawings we saw in earlier posts... there is a reference voltage inside the 1794, so this will be rock solid.

wow! I didn't read those internal drawings closely, but I'm very happy to have seen this in my initial explanation of what's going on with pin 20...

only thing I still do not like is the enormous spread in Idss and hence the needed trimmer. not DIY friendly, but for the die-hard tweakers no issue of course.

this is where LM334 could come in - easier to set off the box...

if all seems worth it at the end of the day, I can pack this next to the next board design. if you than put in a stable 6k resistor or a JFET with trimmer is up to the user so to speak.
 
as I said before, 2SK170 is a pretty poor choice for a JFET CCS (especially here). J201 would work, J202 has too high a Vgs(off)

...though AN103 lists 400uA as out of the ideal range of J201. Even for J202. Here's a summary of requirements vs. difficulties as I see it.

For a well-performing JFET CCS, the goals to hit are:
- Vgs(off) at most half of the voltage the CCS is run at. More brings the CCS in a mediocre operating point as far as its performance goes; preferably, Vgs(off) should be much less that Vd
- Id (current regulated) has to be much less than Idss (not as much as Vgs(off), I think)
- long gate JFETs (very low goss) - J201 (?), J202, 2N4338 (?), 2N4339. Maybe even 2N4393 and others (see AN103 paper). SMD: SST201 (?); SST202.
- RF/VHF/UHF etc. JFETs are also preferred due to the low capacitance (under 10pF preferably for best performance over 1kHz...). BF parts are in this category, therefore a good fit.

But: the Vgs(off) and Idss requirements are somewhat antagonistic, in that a low Vgs(off) - such as less than or equal to 1.2V, so that the 2.4V operating point puts this at high impedance/rejection - brings the Idss in a low range (400uA becomes... high).

I am not sure if I'm doing a good job at explaining this, but in a nutshell, a part with a suitable Vgs(off) will likely not be able to regulate as high a current (too close or higher than the average Idss). Or at least require unfeasible sorting out of too large a pool.

Therefore, a sweet spot is somewhere in there. Not a bad thing.
 
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