Its possible, se this paper http://dafx.de/paper-archive/2004/P_372.PDF
Direct digital pdm (dsd64 up to dsd256) modulated full bridge might be interesting? https://www.diyaudio.com/community/threads/ct7302pl.357501/page-4 , we want to add some digital post filter feedback but we are stuck there, it need to be something ultra fast to proces dsd64 bitstream which need to come from fb postfilter adc, is it possible? Sound is very good even wihout fb. We have plan to do some measurements soon
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Please note that this PowerDAC-S has a 16V 120W linear (regulated) power supply. It has an efficiency of 6.77% so the designer sticks out his neck IMO.
Digital class A.... must appeal to some customers.
Digital class A.... must appeal to some customers.
I saw adders, level detector, noise gate, modulators etc but no explicit reference to level adjustment... maybe I missed it or didn't understand.
What net gain are you hoping for compared to a DAC+Class-D combo?
Measured performance or/and SQ?
If SQ "only", what mechanism do you belive will achieve this?
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For 32 bit word lengths that would require 2^32 = 4,294,967,296 steps per pulse. That is unattainable as the effective frequency has to be sampling_frequency*2^32. For a sampling frequency of 44.1kHz, that works out to 44.1e3 * 2^32 = 189,408,057,753,600 = 189THz!MarcelvdG said:
This is a gross mistake on my part.
Sometimes one gets carried away with too much theory 🙂 Here is an affordable one that simply works in reality:
https://www.audiophonics.fr/en/full...h-50-multiroom-2x80w-4-ohm-black-p-13355.html
It has a DAC only for headphone use.
This one has a price that guarantees instant acceptation by audiophiles (never heard it):
https://support.classeaudio.com/sigma-2200i.html
https://www.audiophonics.fr/en/full...h-50-multiroom-2x80w-4-ohm-black-p-13355.html
It has a DAC only for headphone use.
This one has a price that guarantees instant acceptation by audiophiles (never heard it):
https://support.classeaudio.com/sigma-2200i.html
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No worries, it's easily solved by embedding a coarse pulse width modulator in a noise shaping loop. Power supply and output stage imperfections are the real problems, if you don't use feedback from the analogue signal. That's why the Axign design does use feedback from the analogue signal with a low-latency feedback ADC.
There used to be a post about the TAS5624 and TAS5634 just before this one, but apparently it got removed.
From the datasheet https://www.ti.com/lit/ds/symlink/tas5624a.pdf:
It's essentially a PWM DAC with an analogue class-D amplifier integrated on the same chip. There is a similar picture in https://www.ti.com/lit/ds/symlink/tas5634.pdf See also https://patents.google.com/patent/US7262658B2/en
From the datasheet https://www.ti.com/lit/ds/symlink/tas5624a.pdf:
It's essentially a PWM DAC with an analogue class-D amplifier integrated on the same chip. There is a similar picture in https://www.ti.com/lit/ds/symlink/tas5634.pdf See also https://patents.google.com/patent/US7262658B2/en
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What's SQ meaning? Signal quality?
What net gain are you hoping for compared to a DAC+Class-D combo? On first note I hear so huge and smooth dynamic and clear mids, need to measure things to prove that to myself. Sound is very promising. Another adventage is no opamps, no comparators, no dacs, no etc etc, but directly digitaly modulated h bridge. PDM modulation to me looks like the best modulation in relation to audio domain 20-20k Hz. I might be wrong but my hearing prove that. Now my view on that ddpd concept, it miss an DSD64 post filter adc as a fb loop to make dsd64 input bits correction, its realy chalenge since that reguire something realy utra fast to work on cca 3MHz // 1bit sample rate.
Some interesting dsd software tools, sample rate converters, volume adjustement... etc take a look at source code of the Sox for example, http://archimago.blogspot.com/2021/10/measurements-look-at-dsd-and-using-sox.html for idea.
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How it can be probably done. Dsd64 is 44100Hz x 64 = 2822400Hz, so we probably need feedback ADC with capability to produce DSD64, for example we can find one of 8bit, so 2822400 / 8 = 352800 so it must be fast enought to take sample at every 8th dsd64 input bit, and we than apply input 8bit correction at 352800Hz sample rate, just idea.
Is DSD a necessity or a design requirement by the OP?
It seems this thread is going nowhere by questioning cheap technology that already exists for many years or future high performance stuff with 189 THz CPUs 😀. What is it?
It seems this thread is going nowhere by questioning cheap technology that already exists for many years or future high performance stuff with 189 THz CPUs 😀. What is it?
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Dsd is not a neccesity, I joined in connection with post 15...
Direct pdm modulation is not widely used for audio purposes, there is little on the net on that topic, so someone may find it an interesting solution, unlike pwm modulation. I apologize if the story is unnecessary.
Direct pdm modulation is not widely used for audio purposes, there is little on the net on that topic, so someone may find it an interesting solution, unlike pwm modulation. I apologize if the story is unnecessary.
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Ok, if you are interested, my idea, speaking about pdm modulated class D. An idea came to me how FB could be done. So we have an input DSD64 = 44100Hz x 64 = 2822400Hz rate, we need a fast enough post filter ADC that is able to make a DSD64 8bit sample and pass it back to the input fifo, it means when we divide 2822400 / 8 = 352800Hz so request for a fast rate adc is no more need, instead an adc that is able to sample at 352800Hz sample rate, so for every input dsd64 8 bits we should have adc fast enough to work at sample rate 352800Hz, I think this could be done? And then we need a smart fifo that will be both a fifo and a corrector of the incoming dsd bitstream. At the same time, one counter that will count every 8 sample rates so we know the right timing to request sample from post filter adc synchronously. Adc can be 2x faster too, for example let's say fast enought to do sample at (2 x 352800Hz) so we do two samples at 2 x 352800Hz, then sum them and divide by 2 to have an average sample 8bit value, it will be a bit more precise. Now we have 8bit value and compare with input bitstream 8bit value and make error correction. In theory its easy but in real not since everything must be preciselly synchronysed. My coil arrangement in the head is a little different than those who see only solution trought pwm/pcm, so don't mind! 🙂
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Think about pdm modulated Cuk2 topology! We should than have a less switching noise and no fb reguirement at all.
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Think about pdm modulated Cuk2 topology! We should than have a less switching noise and no fb reguirement at all.
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In the OP I mentioned that algorithms can be used to correct for power supply imperfections and to add functionality like frequency equalisation, the addition of sound effects and mixing. The unrealistic frequency of the timer is a consequence of requiring a comparison for every bit increment until a match is found and the pulse terminates. I was answered that this is NOT necessary as, thankfully for design engineers, a less hardware demanding solution exists already, and ready made ICs are available on the market.
For more information refer to MarcelvdG's posts and other posts.
For more information refer to MarcelvdG's posts and other posts.
There's one for sale on ebay for just $230, but it has the red light failure indicator alledgedly problematic to this unit. Some say there's resistors inside that crack due to a thermal design issue and can be replaced. Too risky for my blood; could be something else I couldnt repair with my limited skills. Others go for $600 - $1500.
Instead of fixing the issue, Denon just quit the model. Too bad, if it was really good as said by its owners. Wouldnt do me a bit of good anyway; price is why I DIY.
Reply to post #36: Actually you first mentioned your ideas for a feedforward control for power supply imperfections in post #4. I'm sure that can reduce the requirements on the supply to some extent, but I haven't a clue what the practical limitations will be.
Wasn't it the PMA-50? I know that one has issues. Bought a PMA-60 new for way under 600 and used it for years without issues. One of the best devices I ever owned.
To avoid having to use an extremely high frequency an auxiliary or intermediate digital to analogue conversion is needed. This refers to what I wrote in the OP. A constant current charges a capacitor and a digital to analogue converter made of a cascade of switchable current sources is made to feed its output current into a resistor. The voltage at the non-ground terminal of the resistor and that across the capacitor are compared resulting in the requird pulse with digitally modulated widths.
Now, to account for the power supply variations (fast and slow), the rail voltages have to be read using an analogue to digital converter. The digital stream is fed into the working algorithms for processing. To correct for processing delays some form of extrapolation of the rail voltages has to be made.
As I coded in the past, and if necessary, I still code, I know algorithms can become extremely complicated. This time, I tried to apply my skill to avoid a DAC and still had to use an auxiliary one!
Now, to account for the power supply variations (fast and slow), the rail voltages have to be read using an analogue to digital converter. The digital stream is fed into the working algorithms for processing. To correct for processing delays some form of extrapolation of the rail voltages has to be made.
As I coded in the past, and if necessary, I still code, I know algorithms can become extremely complicated. This time, I tried to apply my skill to avoid a DAC and still had to use an auxiliary one!