A Basic question about outputs stage driven

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Other things being equal: Does adding a second (parallel) pair of outputs load up the drivers more or the same or less?

eg. If a driver supplies 100mA per rail at full power to the OP device NPN1 (whose gain is lets say 100) if we add a second device in parallel eg NPN2, will the 100mA be divided up between the 2 OP devices or be reduced to 50mA at the driver given the added gain of the second OP device?

Will the driver be loaded more or less by adding more paralleled OP devices given:

1) Total power generated by the Output and
2) The added strain of biasing additional OP devices?

Pls assume this is a class AB push pull output stage with complementary pairs.

Thanks.
 
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This as a very confusing question. Can you make some sketches of what you mean?
For now I would answer:
1 more
2 the two parallel op's conduct both an equal amount of current demanded by the load; if this total demanded current is the same, both op's summed up draw the same from the driver
3 the same for 1), indifferent for 2)
 
I explained it badly...

In simple terms, what does adding more outputs (in parallel to existing OP devices)to an existing design do to the drivers? Lets assume the amplifier needs to be driven into lower loads than it was intended for. Will adding more outputs put additional load on the drivers, or will the beta of the added devices, compensate?
 
...Lets assume the amplifier needs to be driven into lower loads than it was intended for.
Will... more outputs put additional load on the drivers
or will the beta of the added devices, compensate?

Yes,
No.

In more detail -
The problem is the lower impedance load.
You can parallel more outputs to handle that but the drivers still "see" the lower impedance load, reflected thru the outputs, but transformed by their beta.
There may be some improvement because the paralleled outputs mean they are not driven so hard and thus may work at a current where their beta has not dropped off from heavy current effects.
Unless the amp is seriously under specified this won't help too much.

Best wishes
David
 
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Care to amplify? :)

If the load is the same then the extra outputs just split the work between them.
Instead of one OP transistor with, say, 1 amp out and beta 100 so input current 10 mA, now there's 2 OPs now with half an amp out each and 5 mA input each.
Total load on the driver still 10 mA.
At current peaks the OP transistor beta will droop less so less total DC load on the driver, dependent on how over driven the OPs are.
In a conservatively specified amplifier this will be small.
But be aware that the capacitive load on the driver will increase, this may affect stability, perhaps badly, and HF roll-off, probably trivially.
But your question was about added OPs to cope with heavier load.
Here the total load on the driver will increase.

Best wishes
David
 
Think in terms of weight. Two objects always weigh more than one object thereby represent a heavier load regardless of the complexity involved.

This makes sense in terms of driving the bias voltage through multiple functions rather than one. But since the current flowing through the load odds a function of beta of the OP device, more available gain means less current needed from the driver. ... or not?
 
If the load is the same then the extra outputs just split the work between them.
Instead of one OP transistor with, say, 1 amp out and beta 100 so input current 10 mA, now there's 2 OPs now with half an amp out each and 5 mA input each.
Total load on the driver still 10 mA.
At current peaks the OP transistor beta will droop less so less total DC load on the driver, dependent on how over driven the OPs are.
In a conservatively specified amplifier this will be small.
But be aware that the capacitive load on the driver will increase, this may affect stability, perhaps badly, and HF roll-off, probably trivially.
But your question was about added OPs to cope with heavier load.
Here the total load on the driver will increase.

Best wishes
David

I had not considered capacitive loading. Good point. Of this load gets transferred to the VAS, Lots off impact too.

What about at low impedances where beta of the single device started to fall?
 
What about at low impedances where beta of the single device started to fall?

This means straightly - amp is badly designed.
In such a case OPS devices will run out thermally or from secondary breakdown. The one possible case could be switching or tracking rail aka Class-G or Class-H, but this also means more 500 wt output and such an amps must have proper protection system avoiding 2Ohm load (4Ohm bridged) being designed at less output devices quantities.
 
Amplifiers employing negative feedback are impredictable. When you add another output pair, you are changing the output stage and its input capacitance which is seen by the driver stage. This causes a different phase change, which may be enough to cause high frequency oscillations. Please, to save yourself unnecessary expenses, be aware that these oscillations, take place at several hundred kilohertz and are very damaging to the output stage.

My advice, is to make sure no such oscillations take place. The second advice is to test the amplifier using a bulb in series with the amplifier to reduce the mains current in the case of a fault or oscillations.
 

PRR

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....two identical transistors in parallel will exhibit twice the transconductance. ...

Only if each runs the same current as the one. Twice the total current.

Even before we get nonlinearities like beta droop, the OP question has serious ambiguities. "Other things being equal" is rarely true in technology, it's just verbal noise. But later it was said "the amplifier needs to be driven into lower loads" which is NOT "all else equal".

Think about the gain/impedance relationship. Voltage gain and current gain. At the same voltage gain, if you lower the load Z, you must design-in more current gain. However with the lower load Z you may not need the same voltage gain. Some thought is needed. Internet polls may be misleading.
 
Twice OPS devices could provide you with a really huge benefit in terms of dissipating heat while loaded at subs with usually bad current phase shift.
Twice the capacitance sometimes can be also a good benefit based on how EF-triple stabilized. This is a straight way to exclude EF3 instability by using relatively slow OPS devices like MJL21193/4. You just need a powerful driver stage which at some MHz will shoot througt huge BE capacitance of the last devices. This will easily make unstable EF3 to act like stable EF2.
 
So, the capacitance is not an overwhelming concern then?
PRR is right. For the same total current, the net transconductance of the two bipolars is about the same and the net BE capacitance is doubled. So this is like having a single transistor with twice the capacitance. The upside is that the total power rating doubles. There may be other differences, such as ft, which is not usually linear with Ic; so the combined ft is likely to be different from that of a single device. Whether the combined ft is higher or lower depends on the specific transistors. With a transistor where the ft vs Ic is fairly flat and then drops above a certain Ic, like an MJ15022, it may be beneficial to parallel them up.

Capacitance slows the output stage down (mechanically it is like extra inertia). It requires more base charge to change the Ic which means more current from the drivers.
 
Other things being equal: Does adding a second (parallel) pair of outputs load up the drivers more or the same or less?

Transistors understand just one thing: force. In parallel connection, each device will feel a smaller force.

All relationships, such as the amplification factor, depend on energy level. Without the strongly exponential relationships, there would be no transistors and the world would not even exist.

Ceteris paribus is a fundamental principle in mathematics, utterly false when applied to Nature. But linear I/O curves may look beautiful on the paper.
 
N101N said:
Ceteris paribus is a fundamental principle in mathematics, utterly false when applied to Nature.
But in economics, the principle, works! 'Ceteris Paribus' is applied in Partial Differentiation in which, a multivariate function is differentiated treating the remainder independent variables as parameters.

How is Ceteris Paribus applied in amplifier design? Which amplifier designer keeps all the rest of parameters constant while allowing only one to change? Many threads in this forum clearly show, nobody holds all other independent variables affecting transistor operation strictly constant. The use of a Miller capacitance to reduce open loop gain with increasing frequency, is an example. Every designer worthy of its salt, cannot disregard the BASIC fact that transistors are NON LINEAR, no matter what one does to them. The departure from non-linearity is reduced, but it is never removed completely.

The last point about linear relationship is that mathematicians do not look at linear graphs because they look nice, but because, linear relationships are extremely convenient and powerful analytic tools. For instance, during my university course, I remember myself rearranging a formula in a way to be like a linear relationship. The aim, was to obtain a straight line graph for an otherwise non-linear relationship. A straight line with a very high correlation coefficient, of say 0.999, meant the non-linear relationship held.

In the case of amplification, a linear transfer function guarantees no generation of additional harmonics and no intermodulation of present harmonics.

Finally, Series, the branch of mathematics on which Fourier Analysis is based, is well established.

An oddity for the non-mathematically abled, is adding a series of decreasing values infinitely, can result in a finite result, given certain conditions are met. This is known as convergence.
 
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