64fs I2S L/R Separator, help?

[jazz]

Hi,

I need some help. I'm trying to build a small dac to go along with a Pass xpre clone i'm building. Therefore i want the dac to be balanced.

I'm using a cs8412, asynchronous reclocking and tda1543 dacs because i have these at hand. I want to use separate dacs for left and right. Thus the I2S datastream has to be converted in to separate left and right channel datastreams. I found a schematic by Guido (i think, sorry couldn't trace it back just now so no link and i don't wanna post it without permission) but that is for 32 fs whereas i'm using 64 fs.

I couldn't get the 4562 so i'm using cascaded(?) 4517's. I'm getting lost in the data positions (tabs to use). Could someone take a look at the schematic below and tell me how to get it right?

Thanks!

Jazz😕

 

[Cauhtemoc]

That schematic does not use the master clock so it should work nonetheless.

 

[rfbrw]

Needs extending and a little work but this is basically it.

 

[jazz]

Hi,

Thanks for the replies, but i'm not there yet.

Rfbrw, the link you posted is for 48 fs i think. I'm stil getting lost on wheter the scheme i'm using is correct and which data shifts to use.
Also i notice that in that schematic, ws is fed to the multiplexer inverted. What is the reason for that?

Cauthemoc, are you saying the data shifts are chosen correctly for the intended purpose?

thanks
Joris