24-bit R2R DAC using miltiple 16/18/20-bit R2R chips

[Ken Newton]

I was thinking about using a 2x PCM63 current-out DACs. First, which carries 16 MSBs loaded with eg 100ohm (max acceptable value for this chip) and second which carries remaining LSBs loaded with 100ohm/2^16=0,0015ohm. This is proof that this solution is completely unpractical.
Glue logic for this solution is trivial - just 16-bit D flip-flop DATA line delay for first chip, BCLK, LRCLK the same for both chips
Then both voltages should be summed.

Yeah, I will try PCM1704 with resistor or step up trafo followed by quiet tube stage.

Regards
Marek

Exactly, and not just an 1.5 milli-ohm resistor, but an 1.526 milli-ohm net node resistance, including ground path resistance, plus or minus 15 micro-ohms to obtain an arbitrary 1% tolerance. The resulting 2uVRMS fullscale signal would be lost in the PCM63's own noise, let alone that from any following tube stages.

As far as the control logic would be concerned, you forget that audio DACs expect data in 2s complement form. You would have to implement logic to serially insert a copy of each 24-bit word's MSB in the front of the data stream of the 8 LSBs being routed to the lower DAC. Otherwise the lower DAC's output current will be phase reversed whenever the 8th LSB (representing a sign-bit to the lower DAC) differed from the 24-bit word MSB. Not so trivial, I think.

 

[Marek]

Marek,

If you want to go for 24-bit, you can't avoid using a coupling transformer as part of the I/V stage.

You mean step-up trafo? I think it will be my choice too. Using my LL1931 in 1:16 config I can passively gain amplitude to 1,2mA*10ohm*16=192mV ofcourse at the expense of output impedance. This signal amplitude can be put on 6SL7 based SRPP or even lower gain tube.

E

As far as the control logic would be concerned, you forget that audio DACs expect data in 2s complement form. You would have to implement logic to serially insert a copy of each 24-bit word's MSB in the front of the data stream of the 8 LSBs being routed to the lower DAC. Otherwise the lower DAC's output current will be phase reversed whenever the 8th LSB (representing a sign-bit to the lower DAC) differed from the 24-bit word MSB. Not so trivial, I think.

Very important notice! Thank you!
Yes, to ensure right phase of lower DAC there should be additional logic to sample MSB and then negate or not data for lower DAC.