I may be a bit thick as it is past midnight here, but I found the CS4398 datasheet says that 32x f_s SCLK is ok. Actually, I put my EMU 1212m in 192 kHz mode and measured SCLK, and it is only 6.1 MHz.
How can that work? Per f_s cycle, I need to transmit 2x24 bits, and each bit needs one SCLK cycle, i.e. I'd need 48x or 9.2 MHz...
How can that work? Per f_s cycle, I need to transmit 2x24 bits, and each bit needs one SCLK cycle, i.e. I'd need 48x or 9.2 MHz...
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