OpAmp blind test: Burson, ADA4627, NE5534

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The ceramics arrived: 10 grams of 2 op-amps. They are built like a tank.

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One was placed in WHAMMY😎

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I've also started stocking up. I'm waiting for another 10. I think the best are the production years 1987, 1988, and 1989.
 
Earlier this month, Mr. @John Burson sent me a private message and asked if I would be interested in reviewing his discrete op amps in my freshly build AD1862 DAC. Of course I would. He was kind enough to promptly send me two V6 Vivid op amps in exchange for photos and review. Thanks John!

Last December I also got an email about doing this with my P3 which is fitted with a DIP socket.

Unfortunately they shipped me the V7 Classic, not the Vivid.

No problem as it just so happens, I already had both a pair of V7 Classics and Vivids, plus the V6 Classics and Vivid and the V5 and V4. As well as a bunch of others brands.

And I also have one of these...the Lycan, with which you can test the single and double op amps as a headphone amp and preamp...

I've started rolling them in the P3 and I can definitely hear the differences...

BTW- I'm running a Burson Swing DAC as well, currently it has the V7 Vivids, it had the V6 Vivids before. I've listened to a couple of LMs... and still have about eight more.... just started... phew!
 

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Seems the audiophile opamp scene have gone a full circle from IC's to discrete and now back to IC's, VirtualHiFi thinks they have found a solution using lots of opamp IC's in parallel:

Recently, discrete Op Amps became popular.
Since they are built with individual components, many consider them to be better-sounding than the regular integrated Op Amps we know very well.
I agree. I tested many different Op Amps, and the discrete ones always truly shined and sounded superior.
However there is one trick that can be done with regular IC Op Amps - paralleling them
The candy bundle below are yours currently for a discounted €848,70, down from €966,78. :)
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and running them hot (up to 42 mA / opamp):
Ok, where is the catch? Why is it not that popular?
Well, there is a price to pay for that enhanced performance.
First of all, it’s the increased cost. There are multiple Op Amps instead of one, which makes the device cost multiple times higher.
The second thing is size. That increases multiple times as we multiply the number of Op Amps in parallel.
Also, the more Op Amps we parallel, the more power they draw.
So, not only most circuits never were designed to provide the needed power, but excess heat also needs to be dissipated by additional radiators, which increases the cost and size of such Op Amps.
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We have reached a point where the obsession with multiplying chips has overshadowed the original reasons for their sound degradation. After examining micro-images of various op-amps, I found that the Signetics NE5332N is physically twice the size of the TI 5332. Philips offers a version that is 15% smaller, JRC's variant is 25% smaller, and TI's is 50% smaller. Furthermore, the layer deposition on the wafer is thinner, measured in microns. Reducing the die size of an op-amp significantly lowers manufacturing costs, as more chips can be produced from a single silicon wafer, directly enhancing profitability in mass-market products. However, these reductions in size and material deposition often come at the cost of sound performance. Smaller die sizes often mean smaller on-die decoupling capacitors, which are less effective at suppressing noise and maintaining stability in high-frequency applications.The reduced decoupling capacitor size impacts the op-amp's ability to reject power supply noise, leading to greater susceptibility to fluctuations and audible artifacts.
 
I've always wondered about the SoCs used in mobile phones and most of the newer programmable devices. I mean they have DACs so the purpose of the DAC would be missing if you didn't have some analog electronics to drive the outside ( of course, you could pull an Apple and remove all of that... but even so, you still have to have a DAC for the phone function alone, even if the multimedia core no longer drives an analog signal... but at that point, for the phone and microphone you don't need High Fidelity... )

Can you make an analog op amp with VHDL/RDL or do you just copy the core equations and plop it into the models?

I've never programmed an op amp but I figure you would not put it outside of the SoC as the whole point is to put everything into one big piece of silicon.
 
Seems the audiophile opamp scene have gone a full circle from IC's to discrete and now back to IC's, VirtualHiFi thinks they have found a solution using lots of opamp IC's in parallel:
You cannot simply parallel opamps directly, each opamp needs its own local private feedback and the load isolation resistors before combining the outputs. While we can spot some 1k resistors on those boards (on the underside) it is not clear how this would cater for the required specifics for a given circuit.
 
I've never programmed an op amp but I figure you would not put it outside of the SoC as the whole point is to put everything into one big piece of silicon.
You need very different silicon processes and techniques for acceptable analog performance of on-chip opamps (good enough for audio), that's why precision analog functions need to be on a seperate silicon. Divide and conquer.
 
Smaller die sizes often mean smaller on-die decoupling capacitors, which are less effective at suppressing noise and maintaining stability in high-frequency applications.The reduced decoupling capacitor size impacts the op-amp's ability to reject power supply noise, leading to greater susceptibility to fluctuations and audible artifacts.

A howler!
 
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I've always wondered about the SoCs used in mobile phones and most of the newer programmable devices. I mean they have DACs
Rare, integrated ADCs are common for SoC and microcontrollers, but DACs aren't as they use a lot of chip area and can't compete with a real DAC chip using an analog process. And you can simply route PWM to external electronics instead of a DAC output for many purposes (including audio).

Yes, cutting edge high density logic uses entirely different process from analog devices as pointed out above. The bleeding edge is 3nm FinFET process, the only analog stuff on those devices are the VFOs/PLL's for internal clock generation I believe.
 
Hmm.... I did work for a while at a large chip making house... our division was in charge of making SoCs for cell phones. I wrote firmware for the High End SoCs. Lots of ARM cores, lots of stuff, multimedia, memory, modem, fancy cores, very fancy switching, etc...

We had everything shrunk to a single die... including the multimedia module. Also, the modem... which is an analog piece too...

So, we had analog stuff on the die...
 
the only analog stuff on those devices are the VFOs/PLL's for internal clock generation I believe

No, on a high density logic chip there are other full analog blocks, such as for example the high speed serial communication "SER/DES" transceivers, and high speed I/O in general (book link). And there's quite a bit of housekeeping stuff (temperature sensors, ring oscillator health-of-logic-gate monitors, fab process tolerance monitors, etc) also present on the chip, which continuously perform important jobs, but aren't discussed in customer datasheets.
 
It turns out that clocks are a vital part of an SoC in stuff like battery powered portable devices.

Managing clocks is crucial to conserving battery charge... so a huge effort is made to allow clocks to be turned off and on and the resulting electronic "modules" to be turned off as well. That means the modules must be independent... meaning that shutting down the multimedia should not affect the modem... and the DMA should be independent of DDR and NAND. Etc...

There are indeed LOTS of clocks on that die.

The power management firmware is delivered as part of the BSP, hence there is no need for great detail outside of an User's Manual ( no Reference Manual or detailed hardware datasheets ). Even the User's Manual must be minimal on this, otherwise an user could mismanage the operation of the chip and negate all of the careful design work - unless some Intellectual Property were revealed.