This is my first design in progress in LT-Spice and rather unconventional one. The key point is the amp does not use the op-amp in any gain stages and is completely BJT based. After improving the gains of input and output CFP stages using a variant of the bootstrapping technique, I am getting 0.000006% THD@1KHz, yes, that's right - 0.06 PPM. (at least in simulation - best case scenario and I am aware that it is almost impossible to achieve in real-life). I will be glad to publish the design here once the amp is built.
The observation is after the above-mentioned gain improvement, 2nd, 4th, 5th and 8th hormonic peaks in the FFT are pointing downwards. My concern at the moment is, does it indicate a flaw in the design? Should they not be pointing upwards? Or because of RMS this can be ignored? Am I using he best practice? Are there any known impact of such traits in the FFT on the sound quality or musicality.
Your Point-of-View is welcome experts and stalwarts. Your views will help me correct the design flaws, if any. Attached is the FFT diagram
The observation is after the above-mentioned gain improvement, 2nd, 4th, 5th and 8th hormonic peaks in the FFT are pointing downwards. My concern at the moment is, does it indicate a flaw in the design? Should they not be pointing upwards? Or because of RMS this can be ignored? Am I using he best practice? Are there any known impact of such traits in the FFT on the sound quality or musicality.
Your Point-of-View is welcome experts and stalwarts. Your views will help me correct the design flaws, if any. Attached is the FFT diagram
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I have seen artefacts like that with other simulators when the floor of the FFT was too high to properly see the small distortion products, just like in your case. It usually indicates that there is something wrong with the simulation, rather than the circuit.
In LTSpice there is the damn waveform compression that you have to switch off, but I guess you already did that, otherwise it would look worse than this.
It looks a lot like incomplete settling. To improve that, you could make the simulation run longer while using only the last few cycles for the FFT. I usually use the last four cycles for the FFT and apply a Hann window (sometimes incorrectly called Hanning).
If the simulation run time is too long to be practical, you can try getting rid of long time constants to make settling faster. For example, replace AC coupling capacitors with DC voltage sources that have the same voltage across them as a coupling capacitor would have had after settling.
In LTSpice there is the damn waveform compression that you have to switch off, but I guess you already did that, otherwise it would look worse than this.
It looks a lot like incomplete settling. To improve that, you could make the simulation run longer while using only the last few cycles for the FFT. I usually use the last four cycles for the FFT and apply a Hann window (sometimes incorrectly called Hanning).
If the simulation run time is too long to be practical, you can try getting rid of long time constants to make settling faster. For example, replace AC coupling capacitors with DC voltage sources that have the same voltage across them as a coupling capacitor would have had after settling.
Marcel,
Thanks for the reply. It's high time I should watch more videos on LT-Spice fundamentals.
1) In this design the floor starts becoming noisy after 150db because of zeners used in all 3 stages - that is the highlight of the design. In all contemporary designs people are managing to touch the bottom line at 220Db, but in my design it's not attainable. Even with Hann windowing function applied I am able to fathom down to only 160 Db. But that's not the issue. I don't believe a noise above 50k with strength in nano-volts is capable of frying tweeters, hence I don't care. But the noise may cause interference to other device in the vicinity.
2) Changing the Window Size from 300 to 1024 did not help much. With 300 points the E2E simulation time was 59.8 seconds which is slightly reduced to 59.2 with 1024 points. The design is complex with 44 BJTs. Hence, I am not surprised for the large simulation time on i7 processor with 512GB SSD and 16GB RAM.
3) My simulation time is multiple of cycles. I use following parameters. Along with regular Time Domain analysis, some of the parameters are defined for square wave (slew rate), THD, MD, SMPTE, DIM and TIM.
.param Sine_Amplitude=1.414
.param Sqr_Amplitude=1.414
.param ccif_imd_ampl=0.707
.param smpte_imd_ampl=0.707
.param Freq=1K
.param LOAD=8
.param numcyc=10
.param dlycyc=2
.param FFT=8816
.param rccs 70
.param t_edge=.01u
.param tPeriod=1/Freq
.param tOn=tPeriod/2
.param tDelay = tOn * 1
.param vasl 220k
.param simtime=(dlycyc+numcyc)/Freq * 1
.param dlytime=dlycyc/Freq
.param numsampl=simtime/Freq/((simtime/numcyc)*FFT)
.options method=gear
.options maxstep=10u
.options numdgt=7
.options plotwinsize=0
.OPTION itl1=1000
.OPTION itl2=800
.OPTION itl4=600
.OPTION itl6=400
.measure tmp max mag(V(OUT))
.measure BW trig mag(V(OUT))=tmp/sqrt(2) rise=1 targ mag(V(OUT))=tmp/sqrt(2) fall=last
.tran 0 {simtime} {dlytime} {numsampl}
Overall, I believe I am following best practices except the Hann windowing function that I had missed.
My takeaway - Downward pointing peaks is a representation of LT-Spice windowing function (none used) and not a design issue.
Anything you would like to add more?
Prasanna
Thanks for the reply. It's high time I should watch more videos on LT-Spice fundamentals.
1) In this design the floor starts becoming noisy after 150db because of zeners used in all 3 stages - that is the highlight of the design. In all contemporary designs people are managing to touch the bottom line at 220Db, but in my design it's not attainable. Even with Hann windowing function applied I am able to fathom down to only 160 Db. But that's not the issue. I don't believe a noise above 50k with strength in nano-volts is capable of frying tweeters, hence I don't care. But the noise may cause interference to other device in the vicinity.
2) Changing the Window Size from 300 to 1024 did not help much. With 300 points the E2E simulation time was 59.8 seconds which is slightly reduced to 59.2 with 1024 points. The design is complex with 44 BJTs. Hence, I am not surprised for the large simulation time on i7 processor with 512GB SSD and 16GB RAM.
3) My simulation time is multiple of cycles. I use following parameters. Along with regular Time Domain analysis, some of the parameters are defined for square wave (slew rate), THD, MD, SMPTE, DIM and TIM.
.param Sine_Amplitude=1.414
.param Sqr_Amplitude=1.414
.param ccif_imd_ampl=0.707
.param smpte_imd_ampl=0.707
.param Freq=1K
.param LOAD=8
.param numcyc=10
.param dlycyc=2
.param FFT=8816
.param rccs 70
.param t_edge=.01u
.param tPeriod=1/Freq
.param tOn=tPeriod/2
.param tDelay = tOn * 1
.param vasl 220k
.param simtime=(dlycyc+numcyc)/Freq * 1
.param dlytime=dlycyc/Freq
.param numsampl=simtime/Freq/((simtime/numcyc)*FFT)
.options method=gear
.options maxstep=10u
.options numdgt=7
.options plotwinsize=0
.OPTION itl1=1000
.OPTION itl2=800
.OPTION itl4=600
.OPTION itl6=400
.measure tmp max mag(V(OUT))
.measure BW trig mag(V(OUT))=tmp/sqrt(2) rise=1 targ mag(V(OUT))=tmp/sqrt(2) fall=last
.tran 0 {simtime} {dlytime} {numsampl}
Overall, I believe I am following best practices except the Hann windowing function that I had missed.
My takeaway - Downward pointing peaks is a representation of LT-Spice windowing function (none used) and not a design issue.
Anything you would like to add more?
Prasanna
Maybe you already know this, but noise (thermal noise, 1/f noise and shot noise) is not taken into account in ordinary transient analyses. Some simulators have a transient noise feature, but I don't think LTSpice is one of them. When available, it much increases the simulation run time, so it's usually off by default. With a normal transient run, the noise floor you see in the FFT is due to imperfect settling and numerical inaccuracies.
When using the LTSpice noise simulation command, you can get a rather correct noise spectrum referred to the input.
When now knowing the referred noise to the input, you can add a noise generator at the input producing the same amount of noise when doing a transient analysis.
This works quite well in most cases to get a meaningful spectrum.
Hans
When now knowing the referred noise to the input, you can add a noise generator at the input producing the same amount of noise when doing a transient analysis.
This works quite well in most cases to get a meaningful spectrum.
Hans
That's an FFT analysis artifact, a result of an aperiodic (from the FFT window's point of view) component present in the signal.
For example, this simple simulation:
produces this FFT:
Here, I modeled an aperiodic process as a sine source with the frequency so low that not a single period of it fits into the 8ms FFT window. Note that the same effect is present when you have e.g. a slowly charging capacitor somewhere - again, slowly compared to the length of your FFT window. The appearance depends on the level and spectral content of the aperiodic component.
The best remedy is fitting whole periods of all your signals into the FFT window. In the example above, increasing the window in the above simulation from 8ms to 100mS (the period of my V3 voltage source) eliminates the slope completely and shows the harmonics pointing upwards:
However, this remedy is not available for a truly apreriodic process such as a capacitor ( dis-)charging via a resistor. In this case, you may want to delay the FFT (by increasing the "Time to start saving data" parameter) until such time when all aperiodic processes sufficiently settle, and/or replace capacitors with DC voltage sources as @MarcelvdG suggested above.
This is not particularly difficult, esp. in simulation. Try THD @ 6kHz or, even better, 19+20kHz IMD. I'd avoid tests like THD @ 20kHz with out-of-band harmonics though.
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I as well believe that LTSpice has transient noise feature. There is noise measurement feature, but I have read that it is not much useful. I have read experts suggesting shorting the input to the ground and measure the transient noise at the output.
In short, the effect of very slow discharging process of aperiodic component like capacitor in time domain is reflected in frequency domain as spectral slope. Thanks for the update. As a remedy, Marcel as well had suggested to replace large capacitors with voltage sources and batteries, but with your proof-of-concept, I understood the root cause.
Here is the IMD FFT of 19K & 20K frequencies. The attenuation of 1K and 39K is at about -97Db and -71.85 Db respectively, if the frequencies are pinpointed on the Y axis, however, the peaks are close by. The difference frequency attenuation appears to be a good number, but the sum frequency attenuation is not that good. Just acceptable. Some effort is required to push them down within the noise floor to the best possible extent.
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I am not familiar with LTSpice, but I have written FFTs.
In addition to delaying the start of the FFT, you can run the simulation and FFT for longer (millions of points). That will dilute any start-up transients and anything that is not periodic. A modern computer can handle millions of points.
Ed
In addition to delaying the start of the FFT, you can run the simulation and FFT for longer (millions of points). That will dilute any start-up transients and anything that is not periodic. A modern computer can handle millions of points.
Ed
Would be great if you could post an image of such spectrum made relevant by adding a noise generator. Thanks.
To answer the original question, downward spikes imply phase-cancellation between two components of similar magnitude, in the original post there is some sort of spectral leakage causing the main slope, and then various signal spikes - if the phases are different between the signal spike and the spectral leakage they can cancel (typically not by very much since precise cancellation is very unlikely). Once down at the noise floor there's what's called grass, a whole landscape of random spikes, unless spectral averaging is applied - BTW is there a way to do (Welch-style) spectral averaging in LTSpice?
Hans,
here is an old, no frill design. Similar to Elektor Compact Amp published in 1994. Please don't find any quality aspects here.
regrads,
Prasanna
Why would you want it? The noise is not modeled in a transient simulation, and the rest (rounding errors, etc.) is deterministic, so averaging wouldn't help.
This is a hugely complex example, not a real problem, but only when I can't the models for all the needed components.
If not, I will come with a far simpler design.
I'll do the simulations tomorrow morning.
Hans
Ah, that's a good point, I'd forgotten noise analysis was entirely separate. Though averaging would "cut the grass" where it is due to numerical rounding artifacts.
@alexcp,
I think my design is not too bad. By multiplying the simulation period by 100 (1.2s now), I still get both the difference and sum frequencies at ~(-93 Db) buried in the noise floor. I can't get down below it. Afterall, IMD is a by-product of THD. If THD figures are low, then so will be the IMD figures. Here is the FFT.
I have seen expert designers going as low as -150Db but in my design the noise floor is the bottom ceiling. BTH I am hobbyist and tll now designed and built only a couple of amps.
Prasanna