These speculations become especially amusing against the fact that your DAC which you often tout for its alleged localization cues has much higher close-in noise than run-of-the-mill AKM and ESS dacs.
Now you peaked my interest. You designed your own DAC? “1 bit oversampled” sounds like a sigma-delta design. Aren’t they especially sensitive to clock jitter? Do you have specs/schematic to share.
I also designed a sigma-delta DAC for fun using a Spartan S7 FPGA. It worked OK, but I wouldn’t call I HiFi. I’d be interested in your design choices.
You can see pics and links in my clock board thread: https://www.diyaudio.com/community/threads/general-purpose-dac-clock-board.413001/post-7688633
Please be aware that some information is not shown in the first post. You may have to study the whole thread and follow links as they appear. Alao, I can post phase noise plots of my SOA clocks if anyone wants to see them. In addition, the project includes work from multiple designers of which I am only one. The overall implementation is unique to this particular dac.
----------------------------------------------------------------------------------------------------------------------------------------------------------------
Regarding claims that my dac has more phase noise than ESS, there is no proof of that claim. Only measurements of similar yet rather different (and I would argue, inferior) dacs have been compared.
Last edited:
You seem to understand that DSD dacs are sensitive to phase noise. One of the problems that has to be solved is very high performance clocking. The present version of my experimental dac project includes SOA clock oscillators from Acko Labs. The squaring circuit is of my own design.
The output stage is also critical. I am using an experimental prototype SOA transformer based output stage. Unfortunately, I can't share much in the way of details as it is under NDA. Some other people are still working on an alternative output stage design that can be shared publicly and which it is hoped would sound agreeable to most people. There are some builders using Marcel's original output stage board, but with some modifications suggested by me.
The RTZ FIRDAC board itself was designed by MarcelvdG, who works on IC dac design teams for a living. Marcel also published a tube dac design in Linear Audio magazine. What we refer to as PCM2DSD is an FPGA based modulator design from a couple of guys in Poland (for which I did a lot of the listening tests to help optimize the dither problem). PJotr25 is the most active guy for that project. Cestrian designed a compact and simplified clock and reclocker board just for use with Marcel's dac, and for which I provided some assistance.
The thing I found regarding Marcel's RTZ dac board is that it can sound awful at worst, or world class at best. IME it is very sensitive to surrounding circuitry so its that part of the implementation that has been found to make the most difference.
The output stage is also critical. I am using an experimental prototype SOA transformer based output stage. Unfortunately, I can't share much in the way of details as it is under NDA. Some other people are still working on an alternative output stage design that can be shared publicly and which it is hoped would sound agreeable to most people. There are some builders using Marcel's original output stage board, but with some modifications suggested by me.
The RTZ FIRDAC board itself was designed by MarcelvdG, who works on IC dac design teams for a living. Marcel also published a tube dac design in Linear Audio magazine. What we refer to as PCM2DSD is an FPGA based modulator design from a couple of guys in Poland (for which I did a lot of the listening tests to help optimize the dither problem). PJotr25 is the most active guy for that project. Cestrian designed a compact and simplified clock and reclocker board just for use with Marcel's dac, and for which I provided some assistance.
The thing I found regarding Marcel's RTZ dac board is that it can sound awful at worst, or world class at best. IME it is very sensitive to surrounding circuitry so its that part of the implementation that has been found to make the most difference.
You have to forgive me, but my BS detector runs red hot when someone talks about “my DAC”, posts a link to something that’s not a DAC and then hides behind NDA.
The whole thing is an experimental dac spread out over multiple boards. It takes all of it to get good results. If you can't understand that then there isn't much hope for you. No wonder your DSD dac design was hardly hi-fi. Solutions to most of what made your dac sound bad can be found in my Clock Board thread and in Marcel's RTZ dac board thread at: https://www.diyaudio.com/community/threads/return-to-zero-shift-register-firdac.379406/
In summary, sub-ns clock jitter can wreak havoc RF-circuits, especially in the GHz range. In audio it’s neglible and you haven’t provided any evidence apart from subjective opinions and grandiose language. My favorite example of the latter was “samples exist in a Cartesian space of time and amplitude”. Yeah… Duh. also known as a time series.
I’ve wasted enough time on this and my sincere apologies to the original poster for having taken part in hijacking the thread.
I’ve wasted enough time on this and my sincere apologies to the original poster for having taken part in hijacking the thread.
Its trivial to demonstrate in the lab. Professional dac designers know about it, including at AKM and ESS. IC opamp designers know about it too. Its just you that prefers not to know.
I'm going to disagree on the above point too. The context of my comments were about error types and their approximate equivalence in the acquisition of individual samples. In that perspective its more useful to view samples as points in an X/Y graph and evaluate mapping of analog error components due to AN and PN as compared to ideally acquired sample points.
Later when its time to think about DSP processing is when its more appropriate to think of it in terms of a time series.
Hmm, lets look at 16 bit DAC or ADC and a 5kHz signal at full scale. A 1-bit step is 1/32768 of full scale, and the slope of the sinusoidal waveform is about 1 billion LSBs per second (5kHz * 2 * pi * 2^15). So a timing error of 1ns corresponds to upto a single LSB error of amplitude on the sloping/slewing part of the waveform. So if you want jitter-induced error to be significantly below the 16 bit resolution you'd want jitter to be perhaps < 300ps.
Move to a 24bit device and to preserve a full 24 bits means a few ps of jitter matter. The more precise you would like to be in the amplitude domain, the more precise you have to be in the time domain too, in order to represent the signal faithfully to the available bits.
Of course whether the difference between 15 bit and 16 bit accuracy is audible is a separate matter! However if you want true 16 bit performance you are down to the nanosecond regime for jitter. Put another way the actual signal itself intermodulates with the phase noise, transforming it to signal noise. The effect is proportional to the signal level and frequency since those set the slew-rate.
If the phase noise has structure (say the oscillator is pulled slightly by supply rail voltage changes from digital devices loading the rail), then that intermodulated noise will have the same structure - ie. the power rail variation appears on the signal.
I guess an interesting experiment might be to run an audio DAC or ADC from a ceramic resonator rather than a quartz crystal and see what happens?
BTW sample rate doesn't enter into this, just the regularity of the sampling times.
Exactly. And crystal oscillator jitter is typically on the order of tens to hundreds of femtoseconds even for very modest devices. And since it’s stochastic in nature, it’s not likely to compound if you divide the clock frequency using a counter.
EDIT: Cheaper clock generators seem to have jitter in the tens of picoseconds (rather than femtoseconds). Here's one that you can buy for about 5 bucks with a jitter of <70ps. https://www.mouser.com/datasheet/2/472/Si5351_B-2507774.pdf
If you want to go real bargain basement, you can get this one for 77 cents with similar jitter specs (30-70ps): https://www.mouser.com/datasheet/2/268/PL611_01-3500097.pdf
No idea of these are suitable as DAC clocks. Just picked something at random from Mouser. But my point is that I don't think expensive clocks make much difference in audio. RF is a totally different story...
EDIT: Cheaper clock generators seem to have jitter in the tens of picoseconds (rather than femtoseconds). Here's one that you can buy for about 5 bucks with a jitter of <70ps. https://www.mouser.com/datasheet/2/472/Si5351_B-2507774.pdf
If you want to go real bargain basement, you can get this one for 77 cents with similar jitter specs (30-70ps): https://www.mouser.com/datasheet/2/268/PL611_01-3500097.pdf
No idea of these are suitable as DAC clocks. Just picked something at random from Mouser. But my point is that I don't think expensive clocks make much difference in audio. RF is a totally different story...
Last edited:
I get that. I was just thinking of a crude experiment where you shift the channels by a couple of samples to find out of you can hear a difference. That’s obviously many orders of magnitude too much, but it’s the best you can do in the digital domain.
Crystal oscillator phase noise is most commonly specified in a band limited way, say, from 12kHz offset up to some higher limit. That means the jitter or phase noise specification is mostly applicable to 12kHz and above in the audio band. Those oscillators are for RF communications systems and similar applications where more close-in phase noise is not a concern.
For audio data converter use its an entirely different matter. A clock oscillator specified at all for phase noise down at 10Hz offset will only be found in clock oscillators sold as ultra-low phase noise models.
Very few reputable dac designs will use less than the low-cost NDK SDA series of low phase noise clock modules.
For audio data converter use its an entirely different matter. A clock oscillator specified at all for phase noise down at 10Hz offset will only be found in clock oscillators sold as ultra-low phase noise models.
Very few reputable dac designs will use less than the low-cost NDK SDA series of low phase noise clock modules.
Last edited:
You lost me there. What does it mean that jitter is specified in a band limited way? It’s specified in seconds, so it’s a time domain quantity. I’m afraid I don’t understand how the bandwidth comes into the picture. You have an article or something I can read?
Its phase noise that is specified in a band limited way. Phase noise is time-jitter as viewed in the frequency domain. Jitter is usually specified in RMS units, which is fairly useless for dac work. Also, the way jitter is measured makes it impossible to convert to phase noise. However, phase noise can be approximately converted to RMS jitter. What we really need to know is probably more like peak jitter, and or the statistical distribution of jitter around its average value. Unfortunately, the instruments used to measure jitter that way (e.g. expensive oscilloscopes) don't have clocks good enough for measuring audio dac clock jitter in a meaningful way. There are various applications notes that go into more detail about measuring clock performance.
After looking around for awhile, I found a document I thought did a pretty good job discussing phase noise measurement methods. Please see attachment.
Also, a phase noise plot example for an NDK SDA series clock (at a standard audio clock family frequency):
Also, a phase noise plot example for an NDK SDA series clock (at a standard audio clock family frequency):
Last edited: