You can make R5 470 ohms and remove R4, then increase R6 to set the operating point. This way you maintain the symmetry of the output stage, but you use less parts and C1 is used more efficiently.
EDIT: I was responding to the first schematic in the first post.
EDIT: I was responding to the first schematic in the first post.
Right, putting larger resistor on the upper side of bootstrap yields more performance. I have updated in the OP.
I prefer the constant current source version. The bias is less susceptible to drift because of power rail voltage change.
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Maybe this also helps PSRR too, whenever I play music I can hook a scope probe up to the power rails and watch the music there too 🙂
I am not certain. To be that i would like to see at least 20 values for phase between 100KHz and1 MHz.
Are you shure that you can live with about 40w Heat power when the summer comes?
Are you shure that you can live with about 40w Heat power when the summer comes?
My philosophy is to bias it around 300mA if I could, so that the first watt works in pure class A with minimum distortion.
Below, 10KHz -92dB THD at 1W.
10KHz -74dB THD at full power 25W.
Have you ever seen bootstrap for both sides of MOSFETs (double-bootstrap)? I've proposed this in my Zbig1 amp in 2010. Maybe I should publish it in this forum?
Alpha Nirvana amp (by AKSA) has bootstraps on both sides....
This is my version with EXICON mosfets.
I added LTP and Mirror.
It is in Class AB with 300mA bias.
40V single supply.
I added LTP and Mirror.
It is in Class AB with 300mA bias.
40V single supply.
I did something similar a while back, but you are missing some important issues.
1. You must guarantee that the upper gate can be driven lower than the lower gate. Otherwise, you get shoot-through current on the negative clipping. To do this, I added a negative DC offset to the upper gate. See R4+R9+C1
2. The upper gate needs to be loaded so that the gain to each output is similar. See R1.
3. Q3 of the VAS CCS provides some degree of thermal compensation. IE the CCS current varies inversely with temperature and therefore so does the bias on R3.
4. Q5, D1 provide a "Baker clamp" to avoid rail sticking, adjusted for the voltages in this circuit. Also D6+R28.
1. You must guarantee that the upper gate can be driven lower than the lower gate. Otherwise, you get shoot-through current on the negative clipping. To do this, I added a negative DC offset to the upper gate. See R4+R9+C1
2. The upper gate needs to be loaded so that the gain to each output is similar. See R1.
3. Q3 of the VAS CCS provides some degree of thermal compensation. IE the CCS current varies inversely with temperature and therefore so does the bias on R3.
4. Q5, D1 provide a "Baker clamp" to avoid rail sticking, adjusted for the voltages in this circuit. Also D6+R28.
I tried Lateral MOSFET in simulation yesterday. In general, it doesn’t work in class B with this configuration, unless you bias it deep towards class A.
It comes down to its low transconductance. This topology can only produce peak Vgs equal to 2 times of the biased Vgs. Lateral MOSFETs are usually biased around 1v, thus the peaks Vgs it could produce would be 2v, which is not enough.
Good point, this could be the deal breaker for this design. I would like to come up a less intrusive solution.
I have to study this some more but initially I see that D1+D2 prevent the output from getting close to the negative rail so that Q1 is not turned on. That means the negative clip is at about -20V instead of -25V. D3+D4 will prevent the boot strap from pulling Q1 gate more than 1.3 V over the + rail, so the positive clip voltage is reduced about 3V, but I don't think there was a problem on the + side? I don't use MicroCap? (much) so I would have to enter your circuit in LTspice to better see what this will do.
BTW, I would put C4 on the other side of V1 because it does not feed the LTP. When V1 is driven the current in C4 is inverted and attenuated by the OLG.
BTW, I would put C4 on the other side of V1 because it does not feed the LTP. When V1 is driven the current in C4 is inverted and attenuated by the OLG.
If You look at specs for Vishay IRFP140 you see that it is not linear at voltages under 10 volts for a current of 8 amperes. Or lets say about 4v for 3A. The capacitances in the IRF increases also very much at low voltages. They already limit the performance of the amplifier with low output voltage and are the main reason for the - 72 dB or 0,025% distortion at 10 kHz.
If you connect a resistor of R13*R5/R7 = 255k from the output to R12 R24 R25 cross the input stage will act almost as if it has a current generator. Maybe that will reduce the distortion a little bit.
If you connect a resistor of R13*R5/R7 = 255k from the output to R12 R24 R25 cross the input stage will act almost as if it has a current generator. Maybe that will reduce the distortion a little bit.
This one could be interesting to build after 'a simple one watt amp' which is almost ready.
Just asking, you don't have any working prototype yet, only simulations ?
Just asking, you don't have any working prototype yet, only simulations ?