Guys I`m trying to use the old good DVB project Dac board with the latest Amanero Transport ...buut nothing comes out :
I`m trying to use the i/v output on the board as best output , therefore omitted the mosfets outputs , but i think the I2s form the Amanero is not the same as the one used here on the board - on the transport i do use BCK , FSYNC and DATA
Sorry i forgot to add that the Transport DAC ground and TDA1541 are connected also . I saw that there is DEM mode but for ver 4.0 , and i think that the issue at the moment are the I2S signals not been sent to the TDAA1541 correctly . So if i do omit the 74hc02 and try with 22 nf capacitor between pin 16 and 17 will be able to receive the i2s , at the moment TDA has been configured : +5V Time mux TWC
Ask the Amanero guys or owners if the I2S outputis okay for left justified (my post bove). TDA1541A isnot standard I2S input iirc.
You at least should have a sound, whatever it is distorsion, so it coulld be anything.
If you want to use free DEM clock, do not supply the active FDEM and put 470 pF across pin 16/17.
You at least should have a sound, whatever it is distorsion, so it coulld be anything.
If you want to use free DEM clock, do not supply the active FDEM and put 470 pF across pin 16/17.
http://www.audiodesignguide.com/DacNoOverSampling/TDA1541A.pdf
Connect pin 27, notOB/TWC, to +5 V, pin 28, like it's done in the OP's circuit, and the TDA1541A has a TTL compatible I2S input, not left or right justified. You can read on pages 5 and 6 that it's TTL compatible and on page 10, figure 5, that it's I2S.
I suspect all the resistor and resistor-inductor networks between the Amanero and the TDA1541A. The Amanero's 3.3 V CMOS outputs should drive TTL compatible inputs just fine without all that. The bit clock period has to be at least 156 ns.
Connect pin 27, notOB/TWC, to +5 V, pin 28, like it's done in the OP's circuit, and the TDA1541A has a TTL compatible I2S input, not left or right justified. You can read on pages 5 and 6 that it's TTL compatible and on page 10, figure 5, that it's I2S.
I suspect all the resistor and resistor-inductor networks between the Amanero and the TDA1541A. The Amanero's 3.3 V CMOS outputs should drive TTL compatible inputs just fine without all that. The bit clock period has to be at least 156 ns.
Seems unlikely. I doubt there is a more I2S (UM11732) compliant device out there right down to the 0nS hold time.
Anyway, if it were my project, I would try this. The resistors and inductor at the top left are removed, the 74HC02 has been replaced with a TTL compatible 74HCT02. It is somewhat inelegant that DATA/R is connected to BCK rather than grounded or pulled high via a resistor, but so be it.
I have no idea whether the circuitry driving the COSC inputs is correct, but at least I have no reason to believe it isn't. I assume V1+ is somehow connected to VD1+, V1- to VD1-, V2+ to VD2+ and V2- to VD2-, even though the names are different.
I have no idea whether the circuitry driving the COSC inputs is correct, but at least I have no reason to believe it isn't. I assume V1+ is somehow connected to VD1+, V1- to VD1-, V2+ to VD2+ and V2- to VD2-, even though the names are different.
I have the HCT02 and will try it as suggested above , but first will try to re-work the scheme into this variant as it is a working one :
Ok now i`m going to rebuild in this variant , I think that a 22 ohms resistor will not be a bad idea on all of the I2S signals i saw from the original DEM clock that the 12 k resistors where lowered do 6,8k Also guys what will be the best value for the capacitor on 16 and 17 pin ?