The 27Mhz clock is for DIX4192 and SRC4392, and Markw4 means that you want to use the FPGA to use a 24.576Mhz clock to output to DIX4192 and SRC4392
It would make more sense for more people if the FPGA firmware was written to accommodate standard audio clock frequencies. I understand the reason for using 27MHz, but there are no very low phase noise clocks available at that frequency. I would love to try to PWM algorithm but just won't work as is to compete with the high quality reproduction I can get with Iancanada, Andrea Mori, and or Acko Labs ultra low phase noise clocks.
It's open source, so you can modify it as you like, although there is quite a learning curve if you are unfamiliar with Verilog. Verilog is quite quirky.
The sigma-delta modulator itself works fine at somewhat lower clock frequencies, like 22.5792 MHz or 24.576 MHz. The frequency scale of the noise shaping just scales accordingly.
What you would need is an updated interpolation chain. Assuming you start with a clean clock and don't want asynchronous sample rate conversion, you would probably want something with a FIR filter and a CIC filter that changes its interpolation factor depending on the input sample rate, just like @PJotr25 and @olo111 use for their PCM2DSD project.
The 27Mhz clock is for DIX4192 and SRC4392, and Markw4 means that you want to use the FPGA to use a 24.576Mhz clock to output to DIX4192 and SRC4392
I understand what Mark meant, I just don't understand what you meant by: "Can you modify an LX45 filter frequency of 180MHz+to provide a dedicated configuration file".
It's literally the meaning. Are you open sourcing the LX45 source code? This will make modifications easier
The sigma-delta modulator used in versions 1, 2 and 2.1 is probably more suitable than the one from version 3 for use without asynchronous sample rate converter, with a power-of-two interpolation factor. You can find the source code for version 2.1 on the Linear Audio website.
The sigma-delta modulator from version 2.1 (and earlier) has a quantizer sample rate equal to its clock rate, one quarter of its clock rate or one eighth of its clock rate, depending on the mode setting (chaos, PWM4 or PWM8). When you use it with an interpolation filter or chain that interpolates by some integer multiple of eight, you don't get any aliases.
Somewhat familiar with it, but I wouldn't say fluent. Don't think I have the time to work on it though, too much other stuff to do....there is quite a learning curve if you are unfamiliar with Verilog.
BTW, your RTZ dac is sounding very good in stock form, and in SE mode with the only output stage being DC blocking caps and a transformer. Reclocking the inputs with a reclocker free of ferrites and nonlinear caps made a substantial difference to my ears. Imaging is better and instruments more natural sounding.
Since ferrites and caps in this case only impact the clock (MCK) used for reclocking why don't you show the difference on clock signal instead of claim a difference to your ears?Reclocking the inputs with a reclocker free of ferrites and nonlinear caps made a substantial difference to my ears.
Why? Because I don't have a good way of measuring non-PSS, close-in time jitter. Oscilloscopes that can measure jitter are very expensive and don't have clocks with low enough close-in phase noise.
Besides, even if I did have such a measurement tool, the next question from you would probably be, "why don't you show its audible with publication quality ABX DBT?"
Besides, even if I did have such a measurement tool, the next question from you would probably be, "why don't you show its audible with publication quality ABX DBT?"
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Why do you think clock buffer PSU using ferrites or ceramic capacitors would add jitter? Your claim about hearing a difference is as credible as someone claiming that myrtle cable lifters sound better than ones made out of scandinavian birch.
I don't claim to predict why they would. I claim that removing ferrites and nonlinear capacitors, and then using linear caps instead leads to more natural sounding music reproduction as demonstrated on my system here. If other people independently find the same, there there starts to be some statistical power in their reports (at least that would be the view in some areas of science).Why do you think clock buffer PSU using ferrites or ceramic capacitors would add jitter?
Then it may make more sense to try to understand the exact causal mechanisms.
Anyway time will tell, I suppose. Some people will build using my open source boards and we'll see what they have to say. Maybe someone else will want to dig into measuring what it is that makes them sound they way they do. Other than that, I don't care if some people will never be convinced. Some people still think all capacitors must sound the same if they don't measure differently in terms HD/IMD.
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Reclocking has been shown to improve Marcel's RTZ dac already last year so that in itself is hardly news. Some people have enjoyed that improvement for a long time already so you are just late for the party.Other than that, I don't care if some people will never be convinced.
How many people do you think would not find the same but are not telling that? I don't care how many people claim that myrtle cable lifters sound better than ones from scandinavian birch.If other people independently find the same, there there starts to be some statistical power in their reports (at least that would be the view in some areas of science).
Look, I understand your point. However, I am still not persuaded to do work just to satisfy you. Everyone is free to use ferrites or not as they prefer.
You missed my point altogether. I have no interest in your clock buffer or reclocker as I have already been using both for years. If you make unsubstantiated claims I will comment on them if I feel so.
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