Hello I'm brushing off some dust and designing an ADC using the the new ES9822 and I have a few questions about it if anyone here might know the answers.
It's been some time since I've worked with this stuff and I need some intellectual reminders as well as some clarity on the ESS documentation obscurity.
I've been looking at the datasheet here and there are some things I don't understand.
I noticed it mentions the use of a programmable delay to "help with phase compensation when mixing". I have no idea what this is referring to. Could someone clear that up for me?
My next question is about the master/slave modes. I recall the ES9038 having such a thing with the slave mode being superior for some reason. Could someone remind me what the pros and cons of master/slave are?
I've also noticed that the chip has a 2x mode for double the sample rate. I am curious as to the particularities of this as my first thoughts are 2x must be better but obviously it's never that simple. Does anyone know the details and pros/cons of this 2x mode?
Also I'm more used to reproduction than production so can someone inform me of the advantages/disadvantages of i2s/spdif/tdm/dsd output in the context of an ADC?
Lastly are there any particular requirements or quirks with the input to the ADC? I noticed the recommended buffer in the datasheet has some gain reduction and some filtering.
Are there strong reasons for this?
Sorry for all of the questions but this isn't information that is easily available to find if it is available at all.
I would greatly appreciate the insight if possible.
It's been some time since I've worked with this stuff and I need some intellectual reminders as well as some clarity on the ESS documentation obscurity.
I've been looking at the datasheet here and there are some things I don't understand.
I noticed it mentions the use of a programmable delay to "help with phase compensation when mixing". I have no idea what this is referring to. Could someone clear that up for me?
My next question is about the master/slave modes. I recall the ES9038 having such a thing with the slave mode being superior for some reason. Could someone remind me what the pros and cons of master/slave are?
I've also noticed that the chip has a 2x mode for double the sample rate. I am curious as to the particularities of this as my first thoughts are 2x must be better but obviously it's never that simple. Does anyone know the details and pros/cons of this 2x mode?
Also I'm more used to reproduction than production so can someone inform me of the advantages/disadvantages of i2s/spdif/tdm/dsd output in the context of an ADC?
Lastly are there any particular requirements or quirks with the input to the ADC? I noticed the recommended buffer in the datasheet has some gain reduction and some filtering.
Are there strong reasons for this?
Sorry for all of the questions but this isn't information that is easily available to find if it is available at all.
I would greatly appreciate the insight if possible.
IMO that's related to mixing of the converted stream with an external I2S stream. The delay allows to mix samples which correspond to the same time.
I do not think there is any reason a master mode should be superior, provided the clocks in the slave mode are properly timed. But I have done no measurements as my setup has an independent clock generator and does not allow the master mode.
Look at the clock Fig. 4 (page 20) and Table 7 (page 24). IMO the 2x mode either
a) multiplies the MCLK by 2 to obtain the required clock for decimation 128xFs when the MCLK is too low (MCLK 24.5MHz, fs 384kHz, 384*128=49MHz), or
b) cuts the decimation from 128xFs to 64xFs.
I would be surprised if ESS implemented a PLL multiplier for this minor feature. My 2cents b) is the case.
I2S master vs. slave mode probably has no performance implications. However if you plan to use the ADC for measurements DACs are typically I2S slaves so IMO it makes sense to make ADC the I2S master unless separate clock distribution scheme is used. For measurements it is important to have ADC and DAC synchronized (full-duplex I2S) as this IME cleans up the spectrum. If ADC and DAC use separate asynchronous clocks this may result in unwanted spuries on the spectrum.
I didn't ask about it ESS but I guess I2S decoder needed to implement 2 chips stereo i.e. dual mono configuration. ESS datasheets are legendary poor so we can only guess. In the 2x mode I've noticed some HF noise a bit higher than 1x at Fs=384k, and for that reason, I go with NDK 45/49MHz but not with Epcos 22/24 even if Epcos oscillators are noticeable better regarding the jitter. I using 9822 as a master to get the best jitter performance.
It says 2x mode is meant for 768k sample rate but page 24 in the last column doesn't seem to imply that it works beyond 22.5 and 24.5Mhz. Am I stupid?
For DACs at least, that has to do with which device generates I2S clocks (BCLK, LRCK). Usually best if the device most sensitive to clock jitter can be the master. If acting as slave then it may need to use an internal PLL to sync its data output with external clocks. As to whether that might affect ADC sampling jitter, not sure.
Many modern ADCs actually digitize in a way that produces DSD output. However, DSD is not useful if any post processing is required. In that case it must be converted to PCM. When PCM is needed then it is a question of where the conversion from DSD to PCM should take place. Perhaps one could do it with more more precision, say, for exmple, in an FPGA, if needed.
EDIT: Browsing the datasheet a bit, looks like this particular ADC digitizes into RAW mode, as verses directly into DSD. Thus RAW may need to be converted to some standard protocol, which can either be done by the ADC chip or else externally.
TDM is just a way to add more channels to an I2S or SPDIF stream. However, there is only so much total bandwidth available so there may be tradeoffs in that regard.
Gain reduction may be to match gains when multiple ADC chips are used together. ESS has a similar feature in their DACs for gain matching.
Last edited:
The clock is max 49MHz, as stated in the datasheet. That is not enough to reach the decimation clock FSx128 for FS=768kHz, therefore the 2x mode. Also you can use it to run at 384kHz if you have only 24.5MHz. What the 2x mode does internally is not clear to me, as I already wrote.
I don't know your particular ADC, but based on other ADCs:
The filtering is probably meant to prevent aliasing of signals around multiples of the sigma-delta modulator sample rate to audio frequencies.
Old-fashioned professional analogue mixing desks often have a nominal line level of +4 dBu and a clipping level around +24 dBu. Application circuits for audio ADCs often have an attenuation such that full scale corresponds to that +24 dBu. If you have a source with a different level, you can of course adjust the gain accordingly.
If the ADC has a switched capacitor input, you need a driving circuit that can quickly charge the sampling capacitor without behaving non-linearly. I'd stay close to the recommended circuit.
I see. Thanks guys 🙂
Too bad the documentation isn't better.
Difficult to know the optimal configurations.
Too bad the documentation isn't better.
Difficult to know the optimal configurations.
Actually this public datasheet version 0.3 is WAY better than an NDA version 0.2.4 from just a few months earlier 🙂
Do we know if it's a switched capacitor input? That will have implications on the filter RC values.
Figure 4 states that the Analog ADC (what others would call the multibit sigma-delta modulator) always works at 22.5792 MHz to 24.576 MHz, so the only way to change the output sample rate by more than a factor of 24.576/22.5792 is to change the decimation factor. Maybe they kick one decimation-by-two stage out of the decimation chain in this special mode.
Yes, I tried running the ADC conversion at 33MHz (512kHz samplerate at the same clock divider setting as 384kHz, MCLK 33MHz), resulted in increased noise. At lower frequency (16.5MHz) the conversion did not run at all.
Most likely, because they have only 64xFS headroom between the conversion rate and 768kHz output samplerate.
But how does the decimation work for lower samplerates? For 48kHz the scaling is 512xFS, yet the decimation clock is set to 128fs. Are four converted samples averaged, before the 128fs decimation, to improve SNR?
Your guess is as good as mine. There is a CLK IADC that needs to be equal to the clock of the Analog ADC (multibit sigma-delta modulator) and an ADC Decimation Path Clock that can be up to 32 times lower. There must be some basic decimation stage between these clock domains, whether it just adds or averages numbers or does something fancier (n-th order CIC or so) isn't clear to me.
Last edited:
Well, I am really interested on 24.576/22.5792 or even half, while the PN on 45MHz gets not any better 😀
Educated guess: CIC filter stage with an order of at least three. Just averaging four samples and decimating by four gives far too much aliasing of out-of-band quantization noise (only 48.98 dB of suppression at 20 kHz offset from 5.6448 MHz).