For your second output connector you use two stacked power regulators feed from the same positive input. There is a problem. They are not floating with respect to one another and none of the regulators are inverting.
As Mr. Pirinha hints, you can use a second diode where D5 is connected and generate a negative auxiliary voltage, which you can regulate for a negative output voltage with a negative voltage regulator.
Else, use an inverting regulator instead of the lower stacked (positive) regulator.
Some feedback:
- Y capacitor is missing, between transformer secondary GND or HV and primary GND or HV, value similar to C34/C35.
- If EMI filter is supposed to prevent EMI output: C34/C35 have to be placed before CM choke.
- C36 changed to two capacitors, one from each AC lead of diode bridge to one +/- rectifier output, reduces RMS voltage across insulation, thus can reduce creepage and clearance requirements for PCB and transformer (see IEC 60065, IEC 60950).
- Q9 is likely to false trigger the over-current latch, in my experience latches made with bipolar transistors need R and C across base-emitter of both transistors.
- Q7/Q8 and Q5/Q6 are swapped. Emitter follower is the right configuration. I'm not sure 2N3905 is the right complement to 2N3904, maybe it is 2N3906?
- Resistors in series between LO/HO IC outputs and base input of buffers is recommended, as IC output has low impedance clamping diodes to the rails, while the buffers work better with some series resistance to prevent deep saturation due to negative transients coming from gate at turn off of MOSFET/IGBT.
- Overvoltage network (TL431/opto) has no LPF to discard transients (so more noise margin is required).
- Overvoltage network optocoupler shall trigger shutdown latch, not CT/SD pin. Due to the nature of IR(S)2153, for shutdown the CT/SD pin has to be pulled down fast to ground. Slow pulling down will result in abnormal lengthening of cycles (bang!)
- Y capacitor is missing, between transformer secondary GND or HV and primary GND or HV, value similar to C34/C35.
- If EMI filter is supposed to prevent EMI output: C34/C35 have to be placed before CM choke.
- C36 changed to two capacitors, one from each AC lead of diode bridge to one +/- rectifier output, reduces RMS voltage across insulation, thus can reduce creepage and clearance requirements for PCB and transformer (see IEC 60065, IEC 60950).
- Q9 is likely to false trigger the over-current latch, in my experience latches made with bipolar transistors need R and C across base-emitter of both transistors.
- Q7/Q8 and Q5/Q6 are swapped. Emitter follower is the right configuration. I'm not sure 2N3905 is the right complement to 2N3904, maybe it is 2N3906?
- Resistors in series between LO/HO IC outputs and base input of buffers is recommended, as IC output has low impedance clamping diodes to the rails, while the buffers work better with some series resistance to prevent deep saturation due to negative transients coming from gate at turn off of MOSFET/IGBT.
- Overvoltage network (TL431/opto) has no LPF to discard transients (so more noise margin is required).
- Overvoltage network optocoupler shall trigger shutdown latch, not CT/SD pin. Due to the nature of IR(S)2153, for shutdown the CT/SD pin has to be pulled down fast to ground. Slow pulling down will result in abnormal lengthening of cycles (bang!)
Thanks for the correction,
this design has been updated according to your suggestion ...
and you are right what your said ,
that pin CT / SD in IRS2153D if as Shutdown function,
theswitching to GND should be done by quickly,
but in this circuit the Shutdown pin is not in use,
and the function its CT function.
Q11 and C-E opto coupler form a "Resistor variable"
which affects and sense from secondary output voltage side
specified by TL431,
and on the primary side of the tapping of R2 as the current sense.
the final result is the powersupply current and the regulated voltage.
@iyanservice
I see you are in for a 2K smps.
I would go for a better chip at this power which can have feedback in the first place.
I cannot see why you do not make a double secondary winding for feeding the 2 LM2596 this will make life easier for you.
Regulating the IR2153 is not a good idea especially if you are using the RT pin, as EVA said it tends to lower the frequency pulse if not done quickly and this will surely destroy your output fets. The IR2153 is not meant to be regulated. If you want to experiment with it I would rather go for pin 1 and shutting it off rather then anything else.
I see you are in for a 2K smps.
I would go for a better chip at this power which can have feedback in the first place.
I cannot see why you do not make a double secondary winding for feeding the 2 LM2596 this will make life easier for you.
Regulating the IR2153 is not a good idea especially if you are using the RT pin, as EVA said it tends to lower the frequency pulse if not done quickly and this will surely destroy your output fets. The IR2153 is not meant to be regulated. If you want to experiment with it I would rather go for pin 1 and shutting it off rather then anything else.
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The IR2153 has a 555 type oscillator (bouncing between 2 thresholds, 2 comparators feeding 2 latches, NO FLIP-FLOP unlike SG3525 or TL494). This means that sourcing or sinking current from RT/CT pin will lengthen positive pulse and shorten negative pulse, or vice-versa. Frequency regulation with IR2153 is not possible without simulating a variable resistor or capacitor. Frequency regulation is possible with SG3525 and TL494. Next solution is LLC resonant, there are some specific chips for that.
i think you need to read this article to make a LLC resonant converter using ir2153
https://www.infineon.com/dgdl/dt98-1.pdf?fileId=5546d46254e133b401554de8ed5d5e0f
trifolium - Netzteilhandbuch - Beispiel Kapitel 10
after Q12 triggered, Q9 and Q10 will continue conduction even though there is no trigger anymore (locked) and Q11 will pull the CT pin equal to vce sat, when the CT pin is lower than 1/6th Vcc the chip will shutdown
Agree with eva, Q7/Q8 and Q5/Q6 should configured as emitter follower
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