John Curl's Blowtorch preamplifier part II

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I had a look for you.
Meanwell single Vout 48Vdc, SP and RSP series, all with active PFC (local prices, VAT included)
150W=58EURO
320W=82EURO
480W=175EURO
750W=260EURO
1000W=335EURO
1500W=440EURO
2400W=570EURO

George

:eek: :sigh:

For 2 channels with pwr down to 4 ohms = 1000W ps =$400 dollars for one?! and that is only 48vdc ... i need +/-60-70v.

I don't think so.

I'll stay with my <100 dollar analog PS.

Note that the smps tested was $40. There may be room for a quieter smps for under 100 usd. Might not have mil spec quality but..... I'll keep looking.


THx-RNMarsh
 
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Richard
If you are really interested, do search yourself at places less expensive (e.g. Meanwell prices in China can be ¼ to 1/3 of what I wrote above).
Next, please frame the whole picture when thinking of comparing. (You have been adviced for other reliable brands by ticknpop) :
Is it a ready off the shelf product, open construction or enclosed, thermally managed, active PFC, conforming to regulations, what specs, does it have spec’d MTBF (*), is it tested by independent lab for conformance?
Then since you brought that up
<100 dollar analog PS. Really? 1kW, regulated (love to see dynamic behaviour), not dimming the lights when switched on, no talk about 8-10kg weight, size, ect

A reminder, the whole SMPS discussion started by you on noise issues.
(I may post some test data from a guinea pig SMPS I have in the lab)

George
 
Interesting to note is that MeanWell SMPS's are regulated (either voltage or current), as are most SMPS's.

The SMPS by Hypex are unregulated, as are those used by Bruno in the Kii. I can't believe that is a cost issue, so what is behind it?

To me, that should be the discussion: regulated or unregulated SMPS, what is best for audio? Analog PS is ancient technology.
 
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QC is in China. No, professional division (BSS, dbx, Lexicon, DigiTech). No profit in two years. You may start search for another vendor.

Thanks for the corrections. For a bit now have been trying to avoid all Harmon products.

Currently using some German ones for a project underway. Have had two good meetings with their development and engineering folks. Did have to bounce one of their marketing based assistance guys from the project.

Wondering if I should look into starting Elkhart Audio. In reality it turns out two audio amplifier models will cover almost all needs. As the power draw from an AC line is either 2400 or 4800 watts. Offering a 4 channel amplifier or a larger 2 channel version that can max out the power line should do it.

To minimize start up costs Hypex can provide most of the guts and who knows there just might be a sheet metal case vendor looking for new customers. Maybe even a few folks around familiar with producing and marketing them.
 
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May I be so bold to ask (another) tech question?

See attached. Which of the MOSFET capacitances (Ciss, Coss, Crss) are actually loading the output node of this circuit? (Not a trick questione, I genuinely want to know if my view is correct).

thanks for your views,

Jan

OK, updated drawing. Seems clear there is no miller cap, so Cgd is not multiplied but does load the output node. Cgs does not.
Big question is Cds. It hangs off the output node but is the s node high impedance or not?

Edit: s is driven by high impedance (the collector of the BJT) but stays pretty much constant in voltage, meaning Cds will need to be charged/discharged by the output. I think. So does load the output. Yes?

Jan
 

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This is a current output or transimpedance stage, so the load is a voltage load, not a current load. It is already fully loaded by the high impedance at it's output. Any signal will clip the output.

Now if we think of it as if it were in a feedback loop, where the input is changed in order to control the output voltage, then we can think of it as a voltage output circuit with a current load.

It is not loaded by Cds, which will just shunt the MOSFET and make it a more effective cascode at RF. Whether or not it is loaded by Cgs depends on the load impedance, since Icgs depends on Id. Assuming significant voltage swing, Cdg is what is loading this stage.

Ultimately Kirchoff's law applies here. The only path for current to escape from is the gate stopper. All parasitic load currents must go that direction.

There is one quirk of this circuit. It is that current through Cds is forced back through the MOSFET source to it's drain again in a weird kind of recirculation. This means the MOSFET can actually saturate on it's own current at high slew rates without affecting the cascode voltage or output current much.
 
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This is a current output or transimpedance stage, so the load is a voltage load, not a current load. It is already fully loaded by the high impedance at it's output. Any signal will clip the output.

Yes, you need a load impedance to develop any meaningfull output signal, agreed. If you set the DC bias current of the driver stage to the DC current in the current source load you can easily get the output at half supply. In my actual circuit I have a + and - supply so output (with feedback) is zero volts in a load.

It is not loaded by Cds, which will just shunt the MOSFET

It does. One side of the cap moves with Vout (the D side), the other is stationary. So it has to be charged/discharded by the output. I rigged up a quick sim and yes, the current through an added external Cds is just as large as a similar C from D to gnd.

Cdg is what is loading this stage.

Ultimately Kirchoff's law applies here. The only path for current to escape from is the gate stopper. All parasitic load currents must go that direction.

Yes, the size of the gate stopper changes (slightly) the freq response.

The reason why I started doubting this, is when I use different MOSFET parts in the sim, I see NO change in dynamic behaviour, even with MOSFETs with massive Cds! Why not? Cds surely must be in the models??

Jan
 
Jan, the last paragraph in my post explains why Cds doesn't load the circuit as a whole, only the MOSFET. You get the same output gain until the MOSFET saturates enough to disrupt the bias system.

There is a side effect where the MOSFET loaded by it's own Cds develops capacitive currents of capacitive currents through Cgs, which has twice the phase penalty and can be a strict limit on phase margin, but this only happens at very high frequencies.
 
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I recommend building a small signal equivalent circuit (VCCS + caps + gds) in a simulator. This will let you plot the (displacement) current flowing in each of the capacitors, and will also let you .STEP the values of the capacitors over a wide range. So you can see the effect of capacitor C_jkl in isolation.

Don't forget gds (even though lots of MOSFET spice models, meant for SMPS simulations, omit it!). In the absence of any better information, I suggest assuming an "Early Voltage" of 100 volts. In that case

gds = d_ids/d_vds =approx= IDS / (VDS + 100)

where VDS is the dc bias voltage from drain to source in volts, and IDS is the dc bias current from drain to source in amps.
 
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