OK, so conventional wisdom is that you often need a series cap between one component and the next - or one gain stage and the next - to stop any DC offset passing through from the first to the second component / gain stage.
Sure, I understand that DC offset needs to be avoided at the output of a power amp (or the speakers will suffer). But what, really, is the big deal about 'killing' any DC offset between one component and another ... or one gain stage and another? Why does it matter that the signal is a few 10s of mV - or + of what it ideally should be (if there was no DC offset), when it passes into the next component / gain stage?
Thanks,
Andy
Sure, I understand that DC offset needs to be avoided at the output of a power amp (or the speakers will suffer). But what, really, is the big deal about 'killing' any DC offset between one component and another ... or one gain stage and another? Why does it matter that the signal is a few 10s of mV - or + of what it ideally should be (if there was no DC offset), when it passes into the next component / gain stage?
Thanks,
Andy
Many designs have no cap between one stage and the next.
Getting the bias right on each stage, without a cap between one and the other, is an art. More difficult as gain changes over a range of temperatures.
Transistor textbooks tend to include the interstage coupler cap in the examples, as it simplifies the math for the students. Actual production amps didn't, often.
Early designs also used transformers between one stage and the other. As silicon became cheaper than wire, this design feature disappeared. See for example GE transistor manual ed 6, hammond TC-10 tone cabinet on captain-foldback.com
Later designs double or triple the number of transistors to achieve contant currents in front end transistors, instead of a particular operatiing voltage. See Honeybadger build document in the sticky thread above.
One design that sits in the middle is for example Apex AX6. No interstage coupler caps or transformers. It does require defined gain transistors to work properly. Or selection of the idle current resistors for the particular transistors you have, to achieve a mid-rail operating point, as I did. This design is a refinement of many early similar 6 transistor designs, for example Motorola 20W amp, mullard amp, RCA app note examples, various wireless world examples from the 60's 70's, Leak ST70, Armstrong 621, dynaco ST120 etc.
Getting the bias right on each stage, without a cap between one and the other, is an art. More difficult as gain changes over a range of temperatures.
Transistor textbooks tend to include the interstage coupler cap in the examples, as it simplifies the math for the students. Actual production amps didn't, often.
Early designs also used transformers between one stage and the other. As silicon became cheaper than wire, this design feature disappeared. See for example GE transistor manual ed 6, hammond TC-10 tone cabinet on captain-foldback.com
Later designs double or triple the number of transistors to achieve contant currents in front end transistors, instead of a particular operatiing voltage. See Honeybadger build document in the sticky thread above.
One design that sits in the middle is for example Apex AX6. No interstage coupler caps or transformers. It does require defined gain transistors to work properly. Or selection of the idle current resistors for the particular transistors you have, to achieve a mid-rail operating point, as I did. This design is a refinement of many early similar 6 transistor designs, for example Motorola 20W amp, mullard amp, RCA app note examples, various wireless world examples from the 60's 70's, Leak ST70, Armstrong 621, dynaco ST120 etc.
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Thank you. 🙂
The situation I am focussing on is a JFET-based phono stage which consists of:
* 1st gain stage
* passive RIAA circuit
* 2nd gain stage.
It has a coupling cap feeding the Gate of the 2nd gain stage ... I'm wondering whether this can safely be removed ... and if so, what would be the effect?
Andy
The situation I am focussing on is a JFET-based phono stage which consists of:
* 1st gain stage
* passive RIAA circuit
* 2nd gain stage.
It has a coupling cap feeding the Gate of the 2nd gain stage ... I'm wondering whether this can safely be removed ... and if so, what would be the effect?
Andy
Lacking a schematic, you'll need to calculate the operating points of the different stages to see if the AC signal bangs into the ground or + rail at various levels without the cap. This sort of manual calculation is the focus of many early transistor design manuals, although the later ones tend to let the SPICE program do it. I hesitate to recommend a book as
the UK tradition and the US tradition of transistor education were rather different. I've found my best transistor manuals at charity resale shops; the ones I paid $$ for in college bookstores were ****.
the UK tradition and the US tradition of transistor education were rather different. I've found my best transistor manuals at charity resale shops; the ones I paid $$ for in college bookstores were ****.
Depends on gain. If you've got 10mV of offset before 30dB of gain, that's 10V at the output. You'll run out of common mode range if you don't deal with it.
Also in the case of adjustable controls such as volume/balance pots or bass/treble pots, DC across the wipers make the pots go noisy very quickly, and make scratching noises as the controls are adjusted
That's 60db. 30db will give you around 300mv. Many speakers should be ok with that.
Sent from my CP8676_I03 using Tapatalk
Sent from my CP8676_I03 using Tapatalk
'DC offset' could be 10mV (from an opamp stage), or it could be 10V (from a discrete stage). One will adjust the bias of the next stage; the other will redesign the bias of the next stage and probably stop it from operating correctly. I think the OP's mistake is to talk of 'DC offset' as though it will always be small.
Coupling capacitors also help define the LF rolloff of a system. You nearly always want an LF rolloff, and you nearly always will get one. Two choices: design it, or just put up with it being whatever it turns out to be.
Coupling capacitors also help define the LF rolloff of a system. You nearly always want an LF rolloff, and you nearly always will get one. Two choices: design it, or just put up with it being whatever it turns out to be.
Yes - understood. Thanks.
Thank you - I can see that's a key point! The gains are high. 😱
Very true!
Sure! There is another place in the circuit where I could engineer a LF rolloff ... but given all the other comments, it's best if I leave the inter-stage cap in place.
My primary interest in making this post was that I want to temporarily take this coupling cap out of circuit by clipping a wire across it, to help me diagnose a problem with the circuit. From the very helpful answers I've got here, it seems there is no problem doing this on a temporary basis.
Thanks, guys.
Andy
In his defence, I should have been more explicit that I was talking in terms of voltage rather than power.
> a JFET-based phono stage which consists of: * 1st gain stage * passive RIAA circuit * 2nd gain stage. It has a coupling cap feeding the Gate of the 2nd gain stage ... I'm wondering whether this can safely be removed ...
JFETs are 20 cents. Just do it. What is the worst can happen?
Ignoring this unspecified "passive RIAA", I would expect the Drain of the 1st FET to be up at +10V or +20V. The 2nd FET is likely designed for Gate sitting at "zero", where 1V either way will throw the 2nd stage completely out of whack (probably Drain slammed against Source and no output possible). For reasonable parts values, no smoke will happen, and gate damage may be quite insignificant.
JFETs are 20 cents. Just do it. What is the worst can happen?
Ignoring this unspecified "passive RIAA", I would expect the Drain of the 1st FET to be up at +10V or +20V. The 2nd FET is likely designed for Gate sitting at "zero", where 1V either way will throw the 2nd stage completely out of whack (probably Drain slammed against Source and no output possible). For reasonable parts values, no smoke will happen, and gate damage may be quite insignificant.
Aaaaagggghhhh - just as I was getting happy to bypass the coupling cap (to do some trouble-shooting), along comes your post warning me that I might get some (insignificant) gate damage! 😱
Don't know whether the 2nd JFET stage is designed for the Gate sitting at 0v or not ... the Drain of the 1st gain stage (a matched pair of JFETs) sits at half DC supply - so 12v. Then the coupling cap goes between that and the Gate of the 2nd stage (another matched JFET pair) ... I've always assumed this means it also sits at 12v? I'll have to measure it when I get home.
Thanks,
Andy
Matched pair jfets are NOT $.20 and may not be available in leaded packages anymore. Surface mount only. I can't even buy National/Fairchild/SSI J174 anymore, and they were $.38 each right before they were discontinued. I only bought 10 at that price and am regretting it. I used 8 as current limiters and had to pull them back out and replace with J111 to have any stock p-jfets.
So I'd suggest limiting currents with a resistor befure subjecting gate of a jfet to unplanned DC voltages.
So I'd suggest limiting currents with a resistor befure subjecting gate of a jfet to unplanned DC voltages.
Without a circuit diagram, your guess is almost as good as ours. However, 12V at the gate is unlikely; the coupling cap will prevent this (until you short it). Whatever the circuit arrangements, it is likely that shorting a coupling cap will sufficiently change them that deducing the nature of a fault will be rendered more difficult. If you are still hazy about the function of coupling caps and the role and likely values of DC bias then fault tracing may be difficult anyway.andyr said:
Show us the circuit. Describe the fault symptoms. Then we can advise you.
Thanks, DF. The 'fault' is that:
* there is a 390mV signal after the 1st gain stage
* ~40mV after the RIAA network
* the same signal voltage on the input lead of the coupling cap
* but zilch at the Gate of the 2nd gain stage (which is the output lead of the coupling cap).
On the other channel - which is working fine - of course I get a signal at the input of the 2nd gain stage ... and also at the output. 🙂
Doing some measurements last night:
* the coupling cap in both channels measures the same value (well, to <1%)
* the voltage after the coupling cap in the working channel does measure 0v - so the gate of the 2nd stage JFET pair is at 0v.
So I have started the process of unsoldering all the I/O wiring and removing the boards from the case. Then I can get at the underneath and see whether there is a dry solder joint or solder-short, somewhere.
I was hoping that shorting out the coupling cap would've helped me diagnose where the problem is - but that was just naive. 😱 But doing it properly ... I have no doubt that I will be able to find where the problem is.
Thanks everybody for your contributions.
Andy
The coupling cap, or its joints, is bad.
To be super-sure: Put your finger first on chassis (discharge static), then on Q2 Gate. Does it hum/buzz madly? Then Q2 is working, the cap isn't.
Clip-lead almost any other cap across it. Does signal now pass from Q1?
To be super-sure: Put your finger first on chassis (discharge static), then on Q2 Gate. Does it hum/buzz madly? Then Q2 is working, the cap isn't.
Clip-lead almost any other cap across it. Does signal now pass from Q1?
PRR gives good advice. Try it.
I assume you have already checked DC voltages to confirm that all the devices are apparently working?
I assume you have already checked DC voltages to confirm that all the devices are apparently working?