Generally speaking, it is faster to make and measure a functional sample than to debate here. One has to summarize the time already spent.
You really seem to like these thermal trails when you blow at your circuits
and have no use for a reasonable PSRR.
Aaarghhh.
Gerhard
If an op amp is the solution, I want my problem back.
Funny, these audio people. High priests of a low cult.
FYI, Levizon used InterFET IF9030 in his LF/LN amplifier.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS — VOL.55, NO.7, AUGUST2008
IEEE Xplore Abstract - Ultra-Low-Noise High-Input Impedance Amplifier for Low-Frequency Measurement Applications
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Yeah. 300 pF Cin without Miller effect.
Measured at Vds=0 and Vg = -4V, so that both ends
of the channel are nicely reverse biased.
Its much more interesting at Vgs=0V with the
channel-gate varicap closer to max. capacitance.
And there is no such thing as a linear transistor.
It's either square law or exp/log. Any deviation is parasitics.
Use a small part only of their characteristic curve or
linearize them with feedback, even if hidden to save face.
No way around.
regards, Gerhard
The ADA4898 array can easily keep up with that 🙂
0 dB = 1 nV/sqrt Hz,
green = own voltage noise of the amplifier
red = amplifier plus thermal noise of 60 Ohm resistor at its input.
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Richard
That’s strange (or wrong).
The quoted 2nV as an 24bit LSB, implies an ADC Vref of 0.033554432V or a FS Output swing (as vacuphile wrote) of 0.03355443 for a DAC, a hardly unlikely choice.
The amplitude of the LSB depends on the number of bits and on the Reference voltage of the ADC: LSB=Vref / 2^N
So, for N=24:
Vref (V)/ LSB (V)
0.01 / 5.96E-10
0.025 / 1.49E-9
0.033 / 1.97E-9
0.05 / 2.98E-9
0.1 / 5.96E-9
0.25 / 1.49E-8
0.33 / 1.97E-8
0.5 / 2.98E-8
1 / 5.96E-8
2 / 1.19E-7
2.5 / 1.49E-7
3 / 1.79E-7
3.3 / 1.97E-7
5 / 2.98E-7
10 / 5.96E-7
It will eat some of the resolution if it has a Vpp higher than the LSB
George
Always a pleasure having you here. You don't have to bring truffles this time.
I still have a couple of 1259s for you if you can carry stuff back.
The parasitics can include gds in which case you can tune an open-loop JFET phase splitter to null the distortion. Schoeps does it in their microphones. But in general I agree this concept of linearity is flawed, it gets down to picking the right part and bias level for your actual application.
You still see folks cutting the JFET out of one of those TINY mike capsules and subbing an SK170 (this is really a lot of work) only to find the 30pF Cgs kills the gain making it noisier than before.
BTW Gerhard a big customer has requested a "stackable" version of the new 1nV in-amp (AD8229) and it might happen. It would literally be parallel-able with no external components without the monotonic increase in gain.
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This has real value to me. Useful info for the lowest possible noise with a low z source. I think I will get some of the devices to see how to make them work as needed.
THx-RNMarsh
I would be looking for the lowest noise device (at 10Hz) with the largest part of its curve to be most usable to me without feedback.
Afterwards, it can be further linearized by feedback, cascoding, cancellation configurations, etc.
THx-RNMarsh
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I have used the device C's in this way, as you know, on some amplifier designs and it can be made to work very well... distortion cancellation.... even over a fairly wide range.
I often work things backwards..... I set a current level for a stage thru an unknown device first then find the device. With some iterations. When I pre-know the numbers I want to use, I can use a curve tracer to find the device (or spec sheet) which will give me the most linear results in terms of distortion.
BTW --- Can you tell me which opamp from AD or other can give me (without requiring 10-20 of them) <2nV/sqrtHz at 10Hz? A couple or few opamps is Ok but not dozens.
And, which opamp would be best to use along with a IF3602 pair on the input?
THx-RNMarsh
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That must be hard to read. 10 dual packs give 0.22nV/sqrt Hz. 0k, 0.3nV/sHz at 10 Hz.
4th line under FEATURES.
The 300 pF are probably way to optimistic when biasing the FET close to Idss.
You will need the voltage gain of 10, so that the 2nd stage or whatever follows
will not disturb the noise figure. Then expect some nF input capacitance which
is probably not welcome. Then you probably will have to use a cascode stage first
b4 any further processing.
And the FET _pair_ will set you back by sqrt 2, noise-wise.
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I have been told, on good authority, that the Toshiba 2Sk389 is one of the best parts in the world for 10Hz and below noise. One BIG oversight is not shielding the jfet from changes in temperature, due to draft, etc., so adding thermal capacitance and even isolation from air currents is a must.
Ten of anything is out of the question for me. I would also have to evaluate the distortion claim at lower freqs and Not C weighted. What is the noise or distortion if it isnt C weighted?
Then there is still the OPS drive ability -- the most troublesome area for IC's.... as we have discussed here.
THx-RNMarsh
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Here's the link to full paper (PDF):
Ultra-Low-Noise High-Input Impedance Amplifier for Low-Frequency Measurement Applications - ResearchGate
This approach of paralleling low noise IC's is a pretty good one. However, remember that the NOISE Current goes up with paralleled devices. There is no 'free lunch' and you have to keep to low source resistances to get the best performance.
That is really good to know. I just went to my garage stash of parts bins and I have several of the 2SK389-BL. I'll measure them for noise and put it on the curve tracer and compare.
-RM
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