Finally I got some SiC power JFETs. They are quite expensie, so I would not like to damage them.
How do you protect the gate? Do you use Zeners? What is the safe value of gate stopper?
Anatoliy
How do you protect the gate? Do you use Zeners? What is the safe value of gate stopper?
Anatoliy
Thenks to you both!
But does not Zener limit positive voltage, or you use bi-directional one?
Let's pretend it's March 32 today, ok? 😉
According to datasheet it wants positive voltage on gate, it is in cut-off at zero volt. That means we need to protect it from too high negative voltage, against positive voltage it's own p-n junction protects itself.
whatever you say , on March 32. 😉
same as with mighty n32p , when dc connected to some drek in front ....... you need to protect it from excessive positive voltage on gate .
though , even if I didn't had negative experience , my friend scorched few of them , due to few mistakes and wrong parts in preceding circuit
for these , I'm pretty sure that positive peak kill them
I don't have experience in vivo for negative ........... and I also think that you don't need any protection in finished construction , when tests are over
same as with mighty n32p , when dc connected to some drek in front ....... you need to protect it from excessive positive voltage on gate .
though , even if I didn't had negative experience , my friend scorched few of them , due to few mistakes and wrong parts in preceding circuit
for these , I'm pretty sure that positive peak kill them
I don't have experience in vivo for negative ........... and I also think that you don't need any protection in finished construction , when tests are over
The d/s for this 100A part provides plenty of info about G-S SOA. Let's see.
First, we see max Vgs for AC is -10...+15V. For the test conditions specified
(Rg ext. of 1Ω and T≤200ns) that makes forward conduction short pulses of approx. 13A through the gate
Then, in the next table we see Igss specified, as DC, for -10V gs.
Next, on Fig. 5 for DC operation, Ig can be easily allowed to be ≥1A.
On Fig. 8 we see, that gate current can be ~1A to achieve "improvement"
(ha-ha) from 92mΩ to 78mΩ Rdon.
So, clearly, staying well within -10V Vgs limit, and making sure, that
forward Ig current will be well below 1A, this part should perform very well. The rest is just ordinary engineering (I mean, not to test your luck😉).
First, we see max Vgs for AC is -10...+15V. For the test conditions specified
(Rg ext. of 1Ω and T≤200ns) that makes forward conduction short pulses of approx. 13A through the gate
Then, in the next table we see Igss specified, as DC, for -10V gs.
Next, on Fig. 5 for DC operation, Ig can be easily allowed to be ≥1A.
On Fig. 8 we see, that gate current can be ~1A to achieve "improvement"
(ha-ha) from 92mΩ to 78mΩ Rdon.
So, clearly, staying well within -10V Vgs limit, and making sure, that
forward Ig current will be well below 1A, this part should perform very well. The rest is just ordinary engineering (I mean, not to test your luck😉).
The SiC Jfet gates apparently will take a lot of abuse. I have hit them with
some high voltages without damaging them - they just conduct, and as long
as the current isn't too high through them, they still work.
😎
some high voltages without damaging them - they just conduct, and as long
as the current isn't too high through them, they still work.
😎
I've been looking at some of the datasheets, these are big, burly beasts. But don't they need to pull heavy current before they enter their linear region? Like 5A or more?
Thanks Nelson, I am going to use it in gyrator on top of powerful vacuum tube, 420V B+, that means 170V across it, and 250V on gate in respect to ground.
- Status
- Not open for further replies.