I suspect there are others like myself who are in a relatively early stage of circuit design and theory. Not having a good foundation of electrical design, I find myself googling quite a bit and of course there is always a term in a definition that requires more googling. With that in mind, I was thinking that with assistance it would be helpful to others like myself, to have some definitions and FAQs in a single location:
Field Effect Transistor (FET):
"FET transistors are classified into Junction Field Effect transistors (JFET) and Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) transistors."
"A three-terminal Active semiconductor device, where the output current is controlled by an electric field generated by the input voltage... FET uses the voltage applied to its input terminal (called the Gate), to control the current flowing from the source to drain, making the Field Effect Transistor a “Voltage” operated device."*
Vertical Field Effect Transistor (VFET):
"The Junction Field Effect transistor (JFET) is the earliest type of FET. The current flows through an active channel between sources to drain terminals. The voltage applied between gate and source controls the flow of electric current between the source and drain of the JFET. By applying a reverse bias voltage to the gate terminal, the channel is strained, so the electric current is switched off completely. That is why JFETs are referred to as “normally on” devices. The JFET transistors are available in both N-channel and P-channel types."*
Junction Field Effect Transistor (JFET):
"The main function of JFET is to modulate the current between drain and source with variations in applied gate voltage, as it is a voltage-controlled device.
(Vgs =0) If no voltage applied to the gate, it allows maximum current through the source and drain.
(Vgs < 0) With the gate-source junction reverse biased, there should be nearly zero current through the gate connection.
(Vgs > 0) And finally, if the gate-source junction is forward-biased with a small voltage, the JFET channel will “open” a little more to allow greater currents through it,resulting in the transistor damage.
However, the PN junction of a JFET is not built to handle any substantial current itself, and thus it is not recommended to forward-bias the gate junction under any circumstances." Source unknown.
Metal Oxide Semiconductor Field Effect Transistor (MOSFET):
"The MOSFET has four terminals: drain, source, gate, and body or substrate. A MOSFET is also a voltage controlled Transistor, but the main difference between a JFET and a MOSFET is that it has a Metal-Oxide Gate electrode which is electrically insulated from the main current-carrying channel between the drain and source by a very thin layer of insulating material, usually silicon dioxide, commonly known as glass."*
Static Induction Transistor (SIT):
This is a partial description from FirstWatt, the comlete article is
https://www.firstwatt.com/wp-content/uploads/2023/12/art_sit_intro-1.pdf. Of course credit Nelson Pass
Source:
"Source is the terminal through which the majority charge carriers are entered in the FET."*
Drain:
"Drain is the terminal through which the majority charge carriers exit from the FET."*
Gate:
"The gate terminal is formed by diffusion of an N-type semiconductor with a P-type semiconductor. This creates a heavily doped PN junction region that controls the flow of the carrier from source to drain."*
Vgs:
" is the minimum gate-to-source voltage (VGS) that is needed to create a conducting path between the source and drain terminals. It is an important scaling factor to maintain power efficiency." see Wikipedia
idss:
"IDSS (referred to as the drain current for zero bias) is the maximum current that flows through a FET transistor, which is when the gate voltage, VG, supplied to the FET is 0V. When the gate voltage decreases for N-Channel FETs, or increases for P-Channel FETs, the drain current ID becomes smaller and smaller, until after a certain threshold, the transistor shuts off.
The current, IDSS, is important because it's the maximum current that a FET can reach without entering the restricted breakdown region. It is the maximum current in the tolerance range of drain-source voltages, VDS, that can be achieved.
IDSS is referred to as the drain current for zero bias, because the gate-source voltage requires no bias voltage to operate. The gate-source voltage is just zero. No voltage needs to be applied to it. "**
Cascode: Definition/Purpose
Bias:
An initial voltage applied to an output or driver to insure that it is working in the "sweet" spot of it's electrical parameters. Many of the amplifiers on the Pass forum are biased to operate in Class A, see below.
DC Offset:
depending of construction, there will be always some fluctuation of DC offset in real time, but if changes are not abrupt and big, nothing to worry about
in short - amps with NFB tend to behave better (say your Aleph J) than amps without NFB and without any other servo function controlling DC offset ( say M2)
so, if you see DC offset changing slowly in - say - 20mV bracket in time of 1 min, when everything is temp. equilibrium, you're good
and, just a reminder - even if 0mV is desirable value, +/-100mV of DC offset is practically allowed, as industry standard
edit: I know, lack of mileage ...... but your figures of 0.00something mV is, well - not exactly hogwash, but certainly and practically 0mV
Credit ZM
Class A:
By supplying a high enough bias current a transistor will operate in the "sweet" spot of its output and the amplifier will experience no crossover, notch, distortion.
DBT: Description/Proper Usage
Resistance vs Impedance:
* Credit/ Edwin Robedo, Autodesk
** Credit
www.learningaboutelectronics.com