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Old 2nd March 2007, 03:54 PM   #1
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I'm afraid the Hafler and Keroes paper is a piece of "!%*!*?*" that keeps getting quoted endlessly. It's a little overdue that this mess got cleared up.

I just worked out the output Z formula for UL and it essentially gives smooth variation between the triode Zout (or Rp) and pentode Zout as 1/U% ie. (43% UL => U%=0.43 => Zout = Rp_triode/.43)


The effective Mu for the circuit also varies as 1/U% from the triode to the pentode case.

All H & K's chart shows is the effect of a bad mismatch between the tube and output transformer impedance. If the transformer had been properly matched to Zout for each U% on the bottom axis of their chart, one would just get the normal expected performance for a triode with that effective MU and that effective Zout. There is NO optimum U%.

There is nothing special about the 43% or 20% in their charts except for the particular transformer and tube they happened to use for that test. The optimum point on their graph is where it just happens to be matching that tube.

Another serious fault launched by that paper is that one can get away with using the same DC voltage for the screen as for the plate B+. The sharp dropoff in plate current on the left side of all
pentode characteristic curves is due to screen capture of plate current when screen voltage is near plate voltage.

Just using a tap off the output primary for the screen causes distortion to set in seriously just around idle conditions. This means the first watt is literally ruined. Hence the bad rap UL got for sound.

The screen should be lowered by at least 50 to 100 volts below the plate to avoid this distortion. A separate winding for the screens is one way to do this, but now-a-days one can just use a resistive divider off the plate driving a low capacitance MOSFET follower for the screen.

Sorry to sink a few sacred ships, but this needed to be corrected.

Don
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Old 2nd March 2007, 04:20 PM   #2
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Quote:
Originally posted by smoking-amp
----
Just using a tap off the output primary for the screen causes distortion to set in seriously just around idle conditions. This means the first watt is literally ruined. Hence the bad rap UL got for sound.
---
Don

Ouch...We all know wich Watt is the most important...

Arne K
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Old 2nd March 2007, 04:38 PM   #3
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Quote:
Just using a tap off the output primary for the screen causes distortion to set in seriously just around idle conditions. This means the first watt is literally ruined. Hence the bad rap UL got for sound.
Don, do you have any distortion measurements to support this? It seems plausible for sure, so I'd think it would be pretty simple to set up and demonstrate or dispose of (depending on experimental results).
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Old 2nd March 2007, 04:53 PM   #4
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Hi Sy,
I haven't done any measurements yet on this, been busy calculating Mu's and Rp's for UL and CFB. Quite illuminating though. I do have the parts handy however to do some measurements. Give me a few days to set up and I will get back with some spectra. (The weather just cleared up here, sunny and warm thru the weekend, so I may be delayed till next week on this!)

I will use the new Fairchild FQP1N50 MOSFETs I discovered recently to buffer the screen voltage from a resistive plate voltage divider. (only 115 pF input C which will drop to 10pF or so effective in follower mode)
I'm thinking that the best test would be in SE mode so the even harmonics will show up too.

Don
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Old 2nd March 2007, 04:58 PM   #5
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Quote:
Originally posted by smoking-amp
The screen should be lowered by at least 50 to 100 volts below the plate to avoid this distortion. A separate winding for the screens is one way to do this, but now-a-days one can just use a resistive divider off the plate driving a low capacitance MOSFET follower for the screen.
I wondered if it was as easy as all that, so I found an envelope and scribbled on it.

For PP EL84 (convenient example). We would have 10W into 8ka-a. That means 283VRMS across the primary, or 141VRMS at one end. 141VRMS = 200Vpk and that 200Vpk is sitting on the 300V of the HT, so the anode swings to 500V. If our source follower has its drain connected to the 300V HT and we don't like the way input capacitance rises when Vds drops <30V, then it can only swing to 270V. 270V/500V = 0.54. Or to put it another way, we need a potential divider that effectively gives us a maximum of a 54% tap, setting Vg2 = 162V.

Nothing looks unworkable so far...

Edit: From where do you get your Fairchild MOSFETs?
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Old 2nd March 2007, 05:08 PM   #6
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A further thought is that it might be nice to split the AC and DC conditions of the source follower...
Attached Images
File Type: gif ul source follower.gif (6.6 KB, 1918 views)
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Old 2nd March 2007, 05:12 PM   #7
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For a first watt sort of test, where screen current is constant and low, a bypassed voltage divider might be a quick way to test the hypothesis. Not as elegant as the follower schemes, but will certainly show if they are worth pursuing...
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Old 2nd March 2007, 05:13 PM   #8
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One more thought- it strikes me that the distortion from Don's proposed mechanism ought to be second (or at least even) order, yes?
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Old 2nd March 2007, 05:15 PM   #9
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Hi EC8010,

I think I bought mine from Mouser: FQP1N50 500V
http://www.mouser.com/search/refine.aspx?Ntt=fqp1n50
Reasonably priced too.
There is also a P-channel marvel too:
FQP1P50 500V
At least an order of magnitude improved specs over any other HV
P-channel part I've seen (there's only two others)

Yes, a good idea to keep at least 30 V across them for low capacitance.

I think I have one EL84 around, I mostly have 6HJ5 horizontal outputs which require lowered screen voltages anyway. I'll try and find it for testing SE UL EL84 case. I do have some 6L6GC's around too.

Don
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Old 2nd March 2007, 05:15 PM   #10
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Experiment beats theory every time.

My lab still isn't up and running - otherwise there would be FETs under the soldering iron.
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