Ah, thanks..jgedde said:
If the diode is a brazed glass passivated leaded device, the moly (or tungsten) slugs on either side of the silicon should have been visible..moly and tungsten have tce's very close to silicon, I think every lead diode vendor uses one or the other.
A view from the side would shadow very similarly to the second drawing. If it's a simple die with wirebond, I don't know how well the aluminum would show. But from the CH remark, a diode without the plastic moulding is probably a glass passivated device.
I think you're right...mill that puppy...
We gotta know...
Oh, btw...nice work, thank you for all your effort..
ps...any chance of me seeing the film?
Cheers, John
I think we have a definition crisis...roender said:
Diodes I have known.
1. Glass passivated axial leaded. This is constructed by diffusing a wafer to the requirements. Then, sandblast shields made of some plastic, are glued to one side of the wafer in a hexagonal pattern (now that I think of it, it may have been a high temp wax..). All material is blasted away other than under the shields, which are circular..1 amp product was 90 mil diameter (I think..., might have been 60). . Moly or tungsten slugs are silphos brazed to nail head copper leads, this assembly is brazed eutectically to the silicon which has been aluminized...the aluminum alloys to both the moly and the silicon.. This assembly is put on a line which rolls the diodes axially, and an operator or machine syringes a glass slurry over the silicon/moly. It should not go past the moly onto the copper nailhead, but it has to be thick enough to withstand transient surges. This is fired. The diode is complete at this stage, but General Instrument patented the "superrectifier", which included a plastic overmolded case to cover the bead, this made the part far more amenable to automatic insertion....The patent expired umm, 15 plus years ago.
There are many variants of this, leadless auto rectifiers, surface mount units... I believe many manu's, due to the GI patent, used just plastic over the junction...I cannot speak for their longevity.
2. Mesa. Mesa's are planar, the edge has been curved, the intent being to reduce the slope of the edge where the depletion zone reaches the edge...this makes the zone at the edge wider by geometry, lowering the gradient at the surface, forcing the reverse breakdown to occur within the silicon rather than along the edge...makes for more avalanch energy survival capability. I've only used mesa's which required wire bonding..and they are square. I'm not sure if they make mesa based axial leaded with square die, but I recall Powerex or ABB had some kind of mesa process for their 67, 75, and 100 mm diameter product..
3. Regular planar. The depletion zone surfaces on the top of the device, they are square. Some plant extra diffusion along the top breakdown ring to suppress the gradient at the surface, same reasoning as mesa's. (if you examine IR hexfet chips, you see this kind of structure along the outside of the chip, right next to the sawcut).
The planar devices, as you say, can be more expensive if extra steps are taken to passivate...silicon nitride was one of the more expensive ones from what I remember, but it is not permeable to the ionic species, sodium, potassium, etc.
I hope we can find out exactly what device was used in the TT. If axial, I see significant tracking issues as a result of the thermal structure...I was thinking all along that it should have been a planar diode either glued directly to the chip surface (I feared reliability for this, as the epoxy could pull the aluminum off the chip surface), or glued/soldered to a 10 mil thick Al2O3 platform right next to the chip, with wirebonds.
I think clamping a planar device on top of the molded transistor may be the most effective method, even though it may have a longer time constant.
Cheers, John
ps..I love these memory lane trips. Sorry to put all to sleep...
pps.some of the typos are just downright funny.
DouglasSelf said:
I read the app note linked to above last night and it was very interesting. Vishay thermal model their power-FETs with four RC time constants between junction and ambient,something like the TO-3 model I posted. These however do not represent layers of physical construction but are arrived at by curve-fitting to measurements.
Worth reading.
Definitely worth.DouglasSelf said:
Went through this issue with IR product 15 years ago. Ended up punting. Initially had lots of confusion over that pulse-thermal resistance curve set.. I figgered it was put there to provide confusion, and they did their job well.
No matter how well you model it, lateral transport gums the model up...both in the overall structure, and the emmiter finger geometric layout for total area, gain under the fingers and outside (current density), and actual die attach percentage and size of voids.
Using the curve fitting is really the best.. But I'm really gonna hafta review their data collection process, I'm not sure if they measured junction temp accurately.
This method certainly can be adapted to the TT devices.
I think that I'd rather build a widgit to force the die temp to a programmed temperature, and measure the resultant diode parameter. Or, force the die dissipation. That would be far superior as you could try music waveforms.
Cheers, John
roender said:
Cool.
My information is from a while back...21 years ago IIRC.
Here's a link to what I know as a mesa. It took a bit to find it, apparently they've used the same name for a fully planar device as you worked with.
What you have defined as a MESA, I remember as a planar diode with a guard ring.
Perhaps the definitions have changed over the years..It was difficult to find a picture on the web which matched what I remember, almost everything seems to be showing up as you said..
http://www.hitachi-pt.com/products/mechatronics/electronics/pdf/elec_02.pdf
Here's the picture of what I speak of...don't worry about the words or spelling, it appears to be translated badly from japanese.
Cheers, John
Attachments
If we look at the spec for the MUR120 diode series:
Ultrafast 25, 50 and 75 Nanosecond Recovery Times
175°C Operating Junction Temperature
Low Forward Voltage
Low Leakage Current
High Temperature Glass Passivated Junction
Reverse Voltage to 600 Volts
Mechanical Characteristics:
Case: Epoxy, Molded
Weight: 0.4 gram (approximately)
Finish: All External Surfaces Corrosion Resistant and Terminal Leads are Readily Solderable
Lead Temperature for Soldering Purposes: 260°C Max. for 10 Seconds
Polarity: Cathode Indicated by Polarity Band
Marking: MUR105, MUR110, MUR115, MUR120, MUR130, MUR140, MUR160
These are Pb-Free Devices
Stinius
Ultrafast 25, 50 and 75 Nanosecond Recovery Times
175°C Operating Junction Temperature
Low Forward Voltage
Low Leakage Current
High Temperature Glass Passivated Junction
Reverse Voltage to 600 Volts
Mechanical Characteristics:
Case: Epoxy, Molded
Weight: 0.4 gram (approximately)
Finish: All External Surfaces Corrosion Resistant and Terminal Leads are Readily Solderable
Lead Temperature for Soldering Purposes: 260°C Max. for 10 Seconds
Polarity: Cathode Indicated by Polarity Band
Marking: MUR105, MUR110, MUR115, MUR120, MUR130, MUR140, MUR160
These are Pb-Free Devices
Stinius
roender said:
AHA...serves me right...I missed the fact that the blue was glass passivation...I mistook it for diffusion because it was a flat surface..
The picture I presented has the side profile curving exactly as I recall the dice doing.
In your picture, is the glass passivation really filling up the etched valley all the way to the top surface? Or is it a passivation coating, and the dicing saw cuts in the middle of the valley?
Cheers, John
jneutron said:
Firstly, after phosphorus diffusion, the wafer is HF soaked, cleaned and sandblasted.
Then, the wafer is covered with some Si etching resist layer
The wafer is surface diamond-saw-cut, 1/2 of the total wafer depth, into square chips.
Then, the gaps are etched in order to remove any cut-induced strains and filed with a glass based powder compound. The glass is formed at high temperature.
The etching resist layer is then removed and photo resist is applied in order to form the mask for metal layers
After vacuum metal deposition the dicing saw cuts in the middle of the gaps
roender said:
Ah, thank you.
For the normal guys, I've attached a depiction of what we're talking about w/r to mesa's.
The left half is a typical saw cut device. The depletion region (the space where the reverse voltage appears) is the slightly greyer area around the junction. Where this zone hits the surface, there will be a voltage gradient and resultant leakage.
On the right, the mesa topology cuts this zone at an angle. So, the entire voltage is across a longer surface, this reduces the voltage gradient so the resultant leakages...most of a normal device's leakage current is along the edge..
Thanks again, roender..
Cheers, John
Attachments
jneutron said:
Guys, I hate to poop your microelectronics party, but the role of MESA technology has very little to do with the junction leakage currents. MESA is essentially a (cheap and now pretty obsolete, at least for silicon) method to increase the junction breakdown voltage without increasing the capacitance and/or device area.
It's not obvious or easy to get into details, enough to know that in a diffused PN junction, breakdown occurs always ar the junction corners. By etching the structure as in the picture you just posted, the junction corner is removed. If the glass passivation is correctly processed (it's not that easy as it looks) then the MESA junction breakdown approaches the planar junction breakdown (kinda "ideal" case).
It was (and perhaps still is) for Schottky diodes, essentially because it avoids any deep thermal processes, leading to an almost "cold" fabrication process, ideal from the metal semiconductor interface perspective.
For diffused diodes, MESA was pretty abandoned for other more advanced processes as floating guard rings or gated diode. But all these methods are essentially attempting to reduce the corners fringing field to values under the critical field in silicon (around 10e5 V/cm). The same methods apply beyond diodes, to all high voltage devices.
syn08 said:
The devices I used from the waffle packs were mesa for two reasons, as detailed by the manu...
1. Leakage. Surface leakage dominated the device, they used mesa to lower that.
2. Bulk breakdown was forced into the, well, bulk, and away from the edge. This gives higher avalance energy absorbtion capability.
This was according to the vendor. I'm not sure, but for some reason I'm thinking Microsemi..don't hold me to that, it's been a while..
syn08 said:
We basically concur. I really can't see the reason to play with the edges if you can drop a deep well to do the same thing. But since my understanding is 21 years old minimum, I am not up on current trends to that end..However, it appears that roender was actually making the puppies 7 years ago..so obsolete may not be applicable..
And I was buying 3 inch diameter diodes 12 years ago, they had edges that were mechanically bevelled to achieve exactly what I was talking about, very shallow contact angle to spread the surface gradient over a long area for leakage control...I took their word for it of course....
Powerex was the vendor..in Youngswood PA..
Cheers, John
ps...these details are of course, off topic...if you wish to discuss more, perhaps PM?
It seems that this thread becomes of topic and that’s a pity.
The discussion we have had here for a while has been on topic.
It’s of course very interesting to discuss the different ways to produce a diode, but maybe that matter should be move to its own thread? I have read the posts and find them interesting, so keep on the discussion.
The matter we was discussing was where the diode was placed in regards of the thermal transmission, if it was inside the transmission path or outside, that is something that matters, and not how the diode is made. Anyway I think the diode (even if it’s placed outside the thermal transmission path) will track the temp a lot better than the traditional way or the Leach way ( diodes placed in holes drilled in the heath sink) or by placing diodes on top of the packages.
Let’s talk about the TT and how to use them.
John has done a very good job for all of us and we can use the data that he found to implement the TT in a better way.
I have some ideas and I’m sure that a lot of you have.
I’m not going to come with any suggestions before this threat is back on track, but as an example I think I can say that Bob Cordell was quite close in his suggestion. Id =Ic/4.
Stinius
The discussion we have had here for a while has been on topic.
It’s of course very interesting to discuss the different ways to produce a diode, but maybe that matter should be move to its own thread? I have read the posts and find them interesting, so keep on the discussion.
The matter we was discussing was where the diode was placed in regards of the thermal transmission, if it was inside the transmission path or outside, that is something that matters, and not how the diode is made. Anyway I think the diode (even if it’s placed outside the thermal transmission path) will track the temp a lot better than the traditional way or the Leach way ( diodes placed in holes drilled in the heath sink) or by placing diodes on top of the packages.
Let’s talk about the TT and how to use them.
John has done a very good job for all of us and we can use the data that he found to implement the TT in a better way.
I have some ideas and I’m sure that a lot of you have.
I’m not going to come with any suggestions before this threat is back on track, but as an example I think I can say that Bob Cordell was quite close in his suggestion. Id =Ic/4.
Stinius
About preforms: somebody above got it almost right. There are two main reasons why preforms are used.
First, to improve the die attaching/soldering process. This is in particular valuable for steel TO3 cases. Using a preform, the die to case contact can be greatly improved, both in value (lower) and linearity (important for high current devices).
Second, to improve (decrease) the Rthj-c value. In a planar device, heat is always generated at the surface and the heat diffuses to the chip bottom. If we could have infinite thin chips the we wouldn't need preforms. However, a typical silicon chip is around 0.01 inch thick. It doesn't seem much, but it's enough to impact the thermal impedance between the surface and the case... The other obvious solution is to use larger chips. This obviously doesn't make much economic sense. So (usually copper) preforms are used, to artificially extend the chip area. These preforms usually are tray shaped and the tray is almost filled with eutectic (or some times epoxy), to provide a good overall (bottom and sides) thermal contact. The heat now spreads through a much larger area and voila, Rthj-c is decreased.
First, to improve the die attaching/soldering process. This is in particular valuable for steel TO3 cases. Using a preform, the die to case contact can be greatly improved, both in value (lower) and linearity (important for high current devices).
Second, to improve (decrease) the Rthj-c value. In a planar device, heat is always generated at the surface and the heat diffuses to the chip bottom. If we could have infinite thin chips the we wouldn't need preforms. However, a typical silicon chip is around 0.01 inch thick. It doesn't seem much, but it's enough to impact the thermal impedance between the surface and the case... The other obvious solution is to use larger chips. This obviously doesn't make much economic sense. So (usually copper) preforms are used, to artificially extend the chip area. These preforms usually are tray shaped and the tray is almost filled with eutectic (or some times epoxy), to provide a good overall (bottom and sides) thermal contact. The heat now spreads through a much larger area and voila, Rthj-c is decreased.
stinius said:
Hey, there's an echo in here..
dinna I jusss say that???
Anywhoo..
I modelled the chip, they give .625 C per watt as junction to case.
I put in typical die and copper thickness, to get that number requires about a 130 by 130 chip.
With 50 watts input and a 40 degree heatsink, the numbers are:
Junction 103 C
top of baseplate 80 C
So at 50 watts, I'd have the diodes 40C over heatsink but 23C under junction...2/3rds of the thermal excursion..
Course, that 80 C is at the silicon/copper interface..the diode could easily be at 50% excursion...
Anybody know the actual die dimensions?
Cheers, John
syn08 said:
I guess terms have changed over the years..
A preform is a stamped piece of solder or braze..typically 2 to 3 mils thick. Williams metals, indium corp, alpha all sell them.
What you are describing is called a heat spreader, sometimes called a moly tab because they were made of molybdenum, sometimes just copper.
But this stuff is off topic..
Cheers, John
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