The method (due to Middlebrook) from
examples/Educational/LoopGain.asc
is really simple to use. Furthermore, you do not need to fiddle around with the operating point, since the loop stays closed for DC.
Just include an AC source between amp output and feedback network, name the nodes (with F4), do an .ac analysis and type in the simple equation. What you get is exactly the Bode plot of loop gain for estimating stability margins.
There is only one point you need to know: the signal flow in the circuit has to be (almost) unidirectional. In many cases, this is true, since the driving node (e.g., amp output) has much lower impedance than the driven one (e.g. feedback network).
If you do not know this for sure, then you can use the method due to Tian et.al., in LoopGain2.asc. It is almost as easy to use, if you place the more complex plot equation as comment on the schematic.
(Experts say that even this method may fail under rare conditions. Nevertheless, this is all better than opening the loop, since then you change loading of the nodes.)
Matthias
examples/Educational/LoopGain.asc
is really simple to use. Furthermore, you do not need to fiddle around with the operating point, since the loop stays closed for DC.
Just include an AC source between amp output and feedback network, name the nodes (with F4), do an .ac analysis and type in the simple equation. What you get is exactly the Bode plot of loop gain for estimating stability margins.
There is only one point you need to know: the signal flow in the circuit has to be (almost) unidirectional. In many cases, this is true, since the driving node (e.g., amp output) has much lower impedance than the driven one (e.g. feedback network).
If you do not know this for sure, then you can use the method due to Tian et.al., in LoopGain2.asc. It is almost as easy to use, if you place the more complex plot equation as comment on the schematic.
(Experts say that even this method may fail under rare conditions. Nevertheless, this is all better than opening the loop, since then you change loading of the nodes.)
Matthias
matze, this is what I get with the loopgain.asc method.
Seems not working with Mooly's circuit.
But a slight variation of mine, is, upside down, but looks better.
Mooly, I tried your suggestion of making the capacitor huge. In fact, there's a comment in the circuit that I wrote pointing that out. But, as stability margins must be calculated from the loop gain, not the open loop gain, I thought it was just not the proper way...
Why is this?
Seems not working with Mooly's circuit.
But a slight variation of mine, is, upside down, but looks better.
Mooly, I tried your suggestion of making the capacitor huge. In fact, there's a comment in the circuit that I wrote pointing that out. But, as stability margins must be calculated from the loop gain, not the open loop gain, I thought it was just not the proper way...
Why is this?
Attachments
the frequency response is set by the gain of the input pair (gm) and the Miller capacitor. So if you reduce the gm, the capacitor can be reduced to keep the same frequency response. Distortion increases because of the reduced OLG but slew rate increases (reduced capacitance) and therefore susceptibility to slew induced distortion is reduced. You can keep the gain low too with Miller stabilisation, so I think that the CL distortion will be acceptably low still.
Typical gm at 1mA =40mA/V (each device). So to make any significant difference the emitter resistors need to be 25 ohms (halving the gm) and are typically 100 ohms (gm=8mA/V). But with differential pair without a current mirror at the top, this will halve again as you only use the current from the first transistor.
To see the effect feed in a fast square wave (bandwidth limited e.g. by 100kHz RC filter so as to keep some sense of realistic signals), and check what margin you have to slew rate.
Typical gm at 1mA =40mA/V (each device). So to make any significant difference the emitter resistors need to be 25 ohms (halving the gm) and are typically 100 ohms (gm=8mA/V). But with differential pair without a current mirror at the top, this will halve again as you only use the current from the first transistor.
To see the effect feed in a fast square wave (bandwidth limited e.g. by 100kHz RC filter so as to keep some sense of realistic signals), and check what margin you have to slew rate.
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I see you have changed the input bias to +12V + 100k to feed the half voltage into +IN.
Instead use your original R3 & R4 to create a half voltage reference and then use you new R6 to take that ref to +IN.
Once you have these three resistors in place you have an automatic half voltage reference.
Initially make all three resistors the same value. Try 10k and you will find the input impedance is set to 15k where the input transistor has almost no effect on this.
Then step them up to 1Meg. When you get to this value the resistors give an input impedance of 1M5.
The input current of the BC550c has become significant and the input impedance will be <<1M5
Try that and find a reasonable value for those three resistors. (somewhere between 20k and 100k). Later you can change individual resistor values once you understand what the biasing is doing for you.
BTW,
It is worth having a look at the lm3886 datasheet and see how they do the single supply bias voltage using a transistor to give a low dynamic impedance.
Instead use your original R3 & R4 to create a half voltage reference and then use you new R6 to take that ref to +IN.
Once you have these three resistors in place you have an automatic half voltage reference.
Initially make all three resistors the same value. Try 10k and you will find the input impedance is set to 15k where the input transistor has almost no effect on this.
Then step them up to 1Meg. When you get to this value the resistors give an input impedance of 1M5.
The input current of the BC550c has become significant and the input impedance will be <<1M5
Try that and find a reasonable value for those three resistors. (somewhere between 20k and 100k). Later you can change individual resistor values once you understand what the biasing is doing for you.
BTW,
It is worth having a look at the lm3886 datasheet and see how they do the single supply bias voltage using a transistor to give a low dynamic impedance.
The left version (MiniAmp_AB_A_mooly) is already close, only two things.
You need to turn off "AC 1" in the source left to C1. When probing the loop gain, the "probe source" has to be the only active AC source in the circuit.
You should plot V
/V(x).Good luck,
Matthias
Thanks Andrew. I did it this way just for ease of simulation really.
This was my attempt from yesterday. I like Doug Selfs wording on phase margin from his first edition book on power amp design which seems to read (apologies if I have this wrong) that a phase margin of more than 90 degrees isn't possible due to the compensation wrapped around the VAS and that that (the compensation applied) is more than adequate.
(you will need your own models again for the sim and to reset the bias)
Attachments
I attached the loop gain for Mooly's circuit, using the method proposed by matze.
Mooly, your simulation looks so much different.
Mine, the gain starts falling at around 1kHz, yours, at a much higher frequency.
Thanks again you four, john_ellis, AndrewT and matze, for your very helpful explanations, and of course Mooly for your time to make the simulations.
Mooly, your simulation looks so much different.
Mine, the gain starts falling at around 1kHz, yours, at a much higher frequency.
Thanks again you four, john_ellis, AndrewT and matze, for your very helpful explanations, and of course Mooly for your time to make the simulations.
Attachments
It seems to me, we are mixing things here.
The general feedback equation is Aol/(1+Aol*B)
To measure phase/gain margin we need loop gain response, that is:
Aol*B
But we have three different simulations here:
- Mooly, you say your post #40 shows OLG, which is Aol, not Aol*B.
- But my last post is supposed to show loop-gain, not OLG (my simulation's got the same shape as post #40, but lower peak gain).
- So, I don't know what post #46 is.
I've watched the LTSpice video, and It seems like it is that, but the response doesn't look like a loop-gain response (the one in the video does).
I've also read Bob Cordell's description about loop gain, and it seems that my simulation is actually getting loop-gain.
The veio is confusing to me...
"This video illustrates how to use the .AC analysis to look at open loop gain and phase [...] It explains how to break the feedback loop [...] so that the plot the open loop transfer function of the circuit can be obtained and the phase margin measured"
Tthe open loop gain response? We need loop-gain, not OLG.
The general feedback equation is Aol/(1+Aol*B)
To measure phase/gain margin we need loop gain response, that is:
Aol*B
But we have three different simulations here:
- Mooly, you say your post #40 shows OLG, which is Aol, not Aol*B.
- But my last post is supposed to show loop-gain, not OLG (my simulation's got the same shape as post #40, but lower peak gain).
- So, I don't know what post #46 is.
I've watched the LTSpice video, and It seems like it is that, but the response doesn't look like a loop-gain response (the one in the video does).
I've also read Bob Cordell's description about loop gain, and it seems that my simulation is actually getting loop-gain.
The veio is confusing to me...
"This video illustrates how to use the .AC analysis to look at open loop gain and phase [...] It explains how to break the feedback loop [...] so that the plot the open loop transfer function of the circuit can be obtained and the phase margin measured"
Tthe open loop gain response? We need loop-gain, not OLG.
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Open loop gain as we mean it is the gain of the circuit with no signal feedback present. The problem is that to remove the feedback entirely also totally upsets the wanted DC operating conditions of the circuit.
So in my example I take the basic operational circuit and removed just the AC or signal part of the feedback by reducing the 'lower' feedback resistor to essentially zero ohms. That ensures the circuit operates at maximum AC gain.
In this case max OLG gain occurs around 300Hz and is around 74db
Now lets change the simulation back to a transient analysis and apply a really tiny signal to the input, in this example just 10uV peak. Looking at the output voltage we see 60mv peak.
So our gain (OLG) works out at 20log(Vout/vin) which is 75db. If you look at the OLG plot the numbers agree quite favourably. 74 vs 75 db for two different methods.
Bob Cordells method (one of them) is to simply replace the feedback resistor with a massive inductor (to block all AC). The lower feedback return is reinstated. Again the results are virtually the same.
The last image shows the OLG for that method.
So in my example I take the basic operational circuit and removed just the AC or signal part of the feedback by reducing the 'lower' feedback resistor to essentially zero ohms. That ensures the circuit operates at maximum AC gain.
In this case max OLG gain occurs around 300Hz and is around 74db
Now lets change the simulation back to a transient analysis and apply a really tiny signal to the input, in this example just 10uV peak. Looking at the output voltage we see 60mv peak.
So our gain (OLG) works out at 20log(Vout/vin) which is 75db. If you look at the OLG plot the numbers agree quite favourably. 74 vs 75 db for two different methods.
Bob Cordells method (one of them) is to simply replace the feedback resistor with a massive inductor (to block all AC). The lower feedback return is reinstated. Again the results are virtually the same.
The last image shows the OLG for that method.
Attachments
Tthe open loop gain response? We need loop-gain, not OLG.
There is open loop gain (above) and the closed loop gain (the gain when the intended feedback is in place).
This is the closed loop gain.
Attachments
Yes, I understand about how to find the OLG.
Maybe I explained myself badly. Sorry in advance.
I agree with your OLG responses, but aren't they just Aol, and NOT Aol*B?
(Aol*B is what is called open-loop, which is not the same as OLG)
Isn't it the stability margins have to be worked out from the loop gain and NOT the OLG ?
Maybe I explained myself badly. Sorry in advance.
I agree with your OLG responses, but aren't they just Aol, and NOT Aol*B?
(Aol*B is what is called open-loop, which is not the same as OLG)
Isn't it the stability margins have to be worked out from the loop gain and NOT the OLG ?
Not having the English engineering language background, I nevertheless would agree. So just take the Bode plot for OLG (Aol, forward gain of active circuit stages without feedback path), and shift the magnitude down by B (in log scale, corresponding to the feedback "gain", which is smaller than one), assuming it is not complex and constant over frequency.
This highlights a problem of this approach in more advanced applications: if the inverting input notably loads the feedback network, e.g. by its capacity, then it requires further work to find B as function of frequency.
Matthias
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I'm building the circuit on a protoboard.
I feed a 1kHz signal, 100 mV pk, and nothing gets amplified.
After a couple of hours I can't see what I'm doing wrong.
Just to cut things, I removed the output stage (attached built schematic)
I'm using +20V (I'll explain later why).
I measured voltages and currents.
*** LPT (- is the input, + the one which gets feedback)
Vbe- = 11.7V
Vbe+ = 12.2V
Vee = 11.6 V
Vc- = 19.4V
Ic- = 0.6 mA
Ic+ = 1.3 mA
*** VAS transistor colector is 8,8V
*** VAS CCS emitter is 0.56 V, while the base is 1.22V.
The current is 3.72 mA
If I raise the voltage to 24V, I get a sudden raise in current consumption (as measured by my power supply).
Any idea what can I do?
I feed a 1kHz signal, 100 mV pk, and nothing gets amplified.
After a couple of hours I can't see what I'm doing wrong.
Just to cut things, I removed the output stage (attached built schematic)
I'm using +20V (I'll explain later why).
I measured voltages and currents.
*** LPT (- is the input, + the one which gets feedback)
Vbe- = 11.7V
Vbe+ = 12.2V
Vee = 11.6 V
Vc- = 19.4V
Ic- = 0.6 mA
Ic+ = 1.3 mA
*** VAS transistor colector is 8,8V
*** VAS CCS emitter is 0.56 V, while the base is 1.22V.
The current is 3.72 mA
If I raise the voltage to 24V, I get a sudden raise in current consumption (as measured by my power supply).
Any idea what can I do?
Attachments
It sounds like you have either a faulty part around the CCS or a part incorrectly fitted.
One possible conduction path is via the collector base junction and the diodes but that would imply a faulty/wrongly fitted part.
The clues are in voltage measurement. You should not see more than around 0.7 volts across R2 (150 ohm). If you do then the CCS transistor and/or diodes are faulty.
The CCS is able to withstand the full 24 volt supply if needed and so there has to be a basic issue around those components.
The diode chain should level out at around 1.4 volts across the pair.
See whats getting hot by feeling the parts.
One possible conduction path is via the collector base junction and the diodes but that would imply a faulty/wrongly fitted part.
The clues are in voltage measurement. You should not see more than around 0.7 volts across R2 (150 ohm). If you do then the CCS transistor and/or diodes are faulty.
The CCS is able to withstand the full 24 volt supply if needed and so there has to be a basic issue around those components.
The diode chain should level out at around 1.4 volts across the pair.
See whats getting hot by feeling the parts.
Yes, this is the real thing! Reminds me to my own breadboardings already too long ago ...
(It's not meant as joke on your expense. What I find really interesting: one can often smell things early enough before the disaster happens.)
Happy soldering,
Matthias
We've all been there
The current limited supply is a real component saver here although as you are finding out, even 24 volts with just 120ma behind it can generate quite a bit of heat, enough to damage small signal devices.
If you can't immediately find the problem then remove the transistor and check that there is 1.4 volts give or take across the diodes. Check the 150 ohm is OK. Then fit a new NPN making sure that the pinouts are correct.
It doesn't matter at this stage if there are other faults present or not, the CCS should always work correctly.
The current limited supply is a real component saver here although as you are finding out, even 24 volts with just 120ma behind it can generate quite a bit of heat, enough to damage small signal devices.
If you can't immediately find the problem then remove the transistor and check that there is 1.4 volts give or take across the diodes. Check the 150 ohm is OK. Then fit a new NPN making sure that the pinouts are correct.
It doesn't matter at this stage if there are other faults present or not, the CCS should always work correctly.
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