For capacitor ESL, you can at least add an estimate of the inductance of a conductor with length equal to the cap's lead spacing. Most caps don't have much more than that, anyway.
Look through the CDE capacitors. I thought they had some part numbers with 10 uF. Then put those in the applet.
0.1R sounds kind of high, for a C0G ceramic cap's ESR.
Look through the CDE capacitors. I thought they had some part numbers with 10 uF. Then put those in the applet.
0.1R sounds kind of high, for a C0G ceramic cap's ESR.
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In the quest for simulating with parasitics I have to create a first draft PCB. The 100n decoupling caps are just representative at present.
Have changed the parasitics for the ceramics to ESR = 0.01R and ESL to 400pH. This seems to be about right according to Murata. The electrolytics are based upon values from the CDE online app. Only used approximations at present for the smaller caps. Will do more reading on this subject over the coming week.
Here is a more complete schematic. The over load protection is only to protect the devices to allow time for fuse blowing to happen.
Is this a workable schematic?
Have changed the parasitics for the ceramics to ESR = 0.01R and ESL to 400pH. This seems to be about right according to Murata. The electrolytics are based upon values from the CDE online app. Only used approximations at present for the smaller caps. Will do more reading on this subject over the coming week.
Here is a more complete schematic. The over load protection is only to protect the devices to allow time for fuse blowing to happen.
Is this a workable schematic?
Attachments
True, I hadn't considered VGS = 0. The only concern I have with that is that when shorted the drivers are taking the Rail voltage down to 0v via the stopper resistors and would probably over heat if in that state for any time. Some sort of current limit on the drivers may be an idea or maybe run that stage on a very low fuse rating. I know fuses are slow....
Or maybe a signal should go back to the PSU board to turn off the supply rails and then latch in that state. Would be easy to implement as the supply would still be on but the amp disconnected. DC draw would be below an amp with VGS = 0. A relay should be ok turning it off.
And yes D20 is upside down. Thank you.
Edit: Ltspice just gives up with VGS = 0. Also is it possible to have VGS = 0. Do you not need a diode to protect the transistors Q27/28?
Or maybe a signal should go back to the PSU board to turn off the supply rails and then latch in that state. Would be easy to implement as the supply would still be on but the amp disconnected. DC draw would be below an amp with VGS = 0. A relay should be ok turning it off.
And yes D20 is upside down. Thank you.
Edit: Ltspice just gives up with VGS = 0. Also is it possible to have VGS = 0. Do you not need a diode to protect the transistors Q27/28?
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So are you saying that the Gate RC network is more to stop the oscillations starting in the first place. If the oscillations get too violent / prolonged for whatever reason then these networks get destroyed. So actually its better to underrate the resistor as a weak link. Prolonged oscillation = design problem.
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Just how low a wattage and how reliable a fuse would a gate stopper resistor need to be?
This really isn't the place to limit current or fuse a Mosfet as these are charge, not current driven like BJTs.Just how low a wattage and how reliable a fuse would a gate stopper resistor need to be?
Just to clarify, I'm on about the snubbers (forgot the name until just now)going to the rails from the MOSFET gates (eg for U1, R41 and C5). If I'm understanding things correctly, the purpose of these is to damp resonances. Just not sure about how to size them.
And I am struggling to think of a good current limiting system. I don't have much bias voltage at the VAS so options appear to be limited....
Edit: MOSFETs being charge driven has escaped me until now. Will change my thinking.
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Size them as follows:
Disable input RFI filter (set C21 = 0.47 pF). Apply 75 kHz square wave input (2ns rise/fall time) whose amplitude will give output swings 1 volt below the clipping limit. From transient simulation, extract the RMS average current in the Zobel ("snubber") capacitor and extract the RMS average power in the Zobel resistor.
Choose a capacitor whose ripple current rating is >3X the RMS average in this test. Choose a resistor whose dissipation (wattage) rating is >4X the RMS average in this test.
Proposition: A well designed amplifier won't oscillate, not even in bursts, not even with "weird" loads; and equally, a not-well-designed amplifier that does oscillate, deserves to die.
Disable input RFI filter (set C21 = 0.47 pF). Apply 75 kHz square wave input (2ns rise/fall time) whose amplitude will give output swings 1 volt below the clipping limit. From transient simulation, extract the RMS average current in the Zobel ("snubber") capacitor and extract the RMS average power in the Zobel resistor.
Choose a capacitor whose ripple current rating is >3X the RMS average in this test. Choose a resistor whose dissipation (wattage) rating is >4X the RMS average in this test.
Proposition: A well designed amplifier won't oscillate, not even in bursts, not even with "weird" loads; and equally, a not-well-designed amplifier that does oscillate, deserves to die.
They might be good. Or, they might tend to form a resonant LC tank circuit with the inductance of a nearby large electrolytic, et al. In that case, an X7R type would probably be better, since they would probably have more ESR, which would provide some damping.
So I think that the X7R is the preferred (i.e. safest) "blanket recommendation", since not everyone will (or can) really check for the LC resonance situation.
If there happened to be no resonance problem, in a particular case, then an NPO or C0G would be better, because the impedance presented to the power pins would be lower.
And if we could always assume that there would be no resonance problem, then NPO/C0G would be a better blanket RECOMMENDATION.
Just to clarify, I'm on about the snubbers (forgot the name until just now)going to the rails from the MOSFET gates (eg for U1, R41 and C5). If I'm understanding things correctly, the purpose of these is to damp resonances. Just not sure about how to size them.
And I am struggling to think of a good current limiting system. I don't have much bias voltage at the VAS so options appear to be limited....
Edit: MOSFETs being charge driven has escaped me until now. Will change my thinking.
Here you go: (Determining Optimal Snubber Values: )
http://www.diyaudio.com/forums/powe...lm-caps-electrolytic-caps-30.html#post2828689
transistormarkj, gootee,
Thank you for your replies. The information will be very useful. I plan to run the simulation this evening. Wasn't sure how I'd get LTspice to produce signals like the oscillations as they don't exist in the simulation.
As you can tell I haven't read the paralleling film caps with electrolytic caps yet. I plan to so this once I have completed the mammoth task of laying out a PCB and then translating the information back to LTspice. This is going to take sometime as I plan to redraw the schematic as per the PCB with inductors representing the parasitics associated with solder joints and tracks.
I see this as a worthwhile process as I have questions in my head as to whether a given track is too long or terminating incorrectly or should I add some extra decoupling where I have some spare space.
Amp design is a lot of work but good fun and educational. All this parasitics work will hopefully increase the chances of getting a working amp at the end and reduce the chances of wasting money on a flawed design. Btw, still expecting the first prototype to be hacked to pieces.
Mark, I happen to agree with your proposition.
Thank you for your replies. The information will be very useful. I plan to run the simulation this evening. Wasn't sure how I'd get LTspice to produce signals like the oscillations as they don't exist in the simulation.
As you can tell I haven't read the paralleling film caps with electrolytic caps yet. I plan to so this once I have completed the mammoth task of laying out a PCB and then translating the information back to LTspice. This is going to take sometime as I plan to redraw the schematic as per the PCB with inductors representing the parasitics associated with solder joints and tracks.
I see this as a worthwhile process as I have questions in my head as to whether a given track is too long or terminating incorrectly or should I add some extra decoupling where I have some spare space.
Amp design is a lot of work but good fun and educational. All this parasitics work will hopefully increase the chances of getting a working amp at the end and reduce the chances of wasting money on a flawed design. Btw, still expecting the first prototype to be hacked to pieces.
Mark, I happen to agree with your proposition.
Reunited with my books, I see that Cordell says (p.47) that "the ULGF frequency for most audio power amplifiers usually lies between 4 MHz and 40 MHz. ... An amplifier with 40 MHz ULGF will have about 40 dB of negative feedback at 20 kHz"
Self says (p.57) "My own experience leads me to believe that when the conventional three-stage amplifier architecture is used, 30 dB of global feedback at 20 kHz is safe. ... I would say that 40 dB was distinctly risky, and I would not care to pin it down any more closely than that."
To convert Self's NFB dB remarks into ULGF numbers, we begin with the closed loop gain at 20 kHz: 20X (which is 26 dB). Add the feedback factor (30 dB) and you find the open loop gain at 20 kHz: 56 dB. So the ULGF is a factor of {10 raised to the power (56/20)} above 20 kHz. That works out to 12.6 MHz. At the opposite end of Self's range, if the feedback factor is instead 40 dB, then the ULGF is a factor of {10 ^ (66/20)} above 20 kHz, namely 40 MHz.
Thus we can translate this passage in Self's book to be: I think ULGF= 12.6 MHz is safe, and I would say that ULGF= 40 MHz is distinctly risky.
I have not checked your arithmetic, but your logic looks right.
40MHz is "risky", does not mean impossible to stabilise.
I would interpret that as:
one must be very thorough to examine all loops that could become unstable for all the loads that could occur for all the operating conditions that will occur, if one wants to push the ULGF towards 40MHz.
40MHz is "risky", does not mean impossible to stabilise.
I would interpret that as:
one must be very thorough to examine all loops that could become unstable for all the loads that could occur for all the operating conditions that will occur, if one wants to push the ULGF towards 40MHz.
Been a bit quiet of late... Been busy progressing this project.
Thank you for the replies regarding ULGF. I have read sections in both books over and over and now I think I have a grasp of the concept now.
Have a couple more questions....
1) Regarding parasitics what would be a good series resistance value for the DC supplies in LTspice? I have read that 2.6R is a good value but does this take into account the reservoir caps? If I use 2.6R I get a peaking in the closed loop response just before roll off. Not good. Can solve this by slowing the amp down but this results in an increase in THD at 20K.
2) Would the 2sc1845/2sa992 transistors be better to use than the 2n5551/5401 pair? The specs look better on paper for the 1845/992s. However, in LTspice the THD is greater for the 1845/992 pair. Is this just a case of the different models and reality would be different? (I have stocks of both)
I will be posting PCBs and updated schematics soon.
Thank you for the replies regarding ULGF. I have read sections in both books over and over and now I think I have a grasp of the concept now.
Have a couple more questions....
1) Regarding parasitics what would be a good series resistance value for the DC supplies in LTspice? I have read that 2.6R is a good value but does this take into account the reservoir caps? If I use 2.6R I get a peaking in the closed loop response just before roll off. Not good. Can solve this by slowing the amp down but this results in an increase in THD at 20K.
2) Would the 2sc1845/2sa992 transistors be better to use than the 2n5551/5401 pair? The specs look better on paper for the 1845/992s. However, in LTspice the THD is greater for the 1845/992 pair. Is this just a case of the different models and reality would be different? (I have stocks of both)
I will be posting PCBs and updated schematics soon.
Hello mcd99uk. 2.6R will cause significant voltage drop. In case of capacitive load there will be phase shift much lower on freq. band. It can be used for testing bad conditions I think. But in reality, with good classic power supply it is hardly expected such ohmic lose. 0.26 maybe, but still with good caps and robust wiring it will be lower. Please consider that electrolytic resistance is lowered by paralleling. Inductance (much bigger problem) is commonly solved by bypassing and decoupling as you know.
Every experienced diy builder claims that reality is different from spice world. Do not stick to zero hunt (thd) but use what experts claims about what is good for sound (it is that purpose, isn't it?) Later you will have your knowledge about your concept and schematic when it comes to daylight.
You are doing praiseworthy engineering with your design. Hardly wait for final results.
One thing to try in simulation, is to add a 220 uF, 160 volt electrolytic capacitor on the amplifier PCB itself, between +VCC and -VCC, physically located right at the drain terminals of output devices U1-U4. You can estimate the capacitor's ESR from the (tan delta @ 120 Hz) info in the datasheet. You can estimate its ESL from appnotes @ Cornell Dubilier.
(this 220 uF capacitor) offers 10,000 hour lifetime at high temperature, 1.95A ripple current, low dissipation factor (0.15), and is less than an inch tall.
Why 220 uF? Its capacitive reactance at a frequency "just before roll off of the closed loop response" is small with respect to 2.6 ohms. You might tinker with applying more than one of them in parallel, to reduce ESR and ESL. (You might find 160V insufficiently conservative?)
Why across +VCC and -VCC? For one thing, it doesn't pollute ground.
Oh, and you need a pair of 1N5404 diodes (3 amps rating), from +VCC to FB and from -VCC to FB. Presumably the power supply board has another pair of 15 amp diodes from +VCC to gnd and from -VCC to gnd. See Self 5th edition pp. 455-6, and Cordell 1st edition p.325.
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why is this an advantage?
Have you studied the route that the speaker current takes when passing from the +ve supply rail and back to the supply for one half of the AC audio signal?
Have you done likewise for the other half of the AC audio signal?
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