Your are of course correct. I know the diode choice is very significant. I have yet to research what is available and what spice models are available.
Am i right in thinking ltspice default is an ideal diode?
Like the MMSD4148 diode. Its SMT but i don't mind SMT soldering. And available from farnell @ around 10p each. Have you any recommendations for good diode for this prurpose SMT or through hole?
Many thanks
Paul
I don't think it's ideal, based on some quick simulation testing. I'm not sure but it might just be a type that resembles a generic diode on some particular type of IC die, which is what spice was originally developed to simulate.
Whatever you use, it might be wise to do some testing that specifically tries to investigate the model itself. Some of them are extremely unrealistic. In particular, I remember using a 4148 model from somewhere that was "quite optimistic". There should be several models available from different manufacturers. You should probably at least compare them, in a text editor, to see if any stand out as having parameters that are a lot different than most of the others.
I don't know enough to recommend any particular diode. Sorry.
Strange I didnt get email notification from this thread which I happen to be interested in as I primarily focus on CFB topologies. I see some peaking in closed loop response which might mean problems. Have you tried to use lag compensation, just RC from vas to ground or RC from vas to the rails from each vas. Usually lag comp means wider bandwith with this topology. I have never used a emitter enhanced vas in this topology so Im rusty here but using baxandall vas and no error correction I manage about the same THD figures.
Can you post the .asc file.
Can you post the .asc file.
Hello Manso,
The peaking response was caused by adding the pure capacitive load to test stability. The peaking appears to come from the HEC when driving capacitive loads with no L//R filter. It can be corrected easily but slows the HEC down.
I have not used lag comp on the vas as in Self's book he says that it is a brutal way to treat a VAS. That's why I went for a resistive load back to the IPS output. This seems to reduce the harmonics at the VAS.
The distortion figures can be made much better with the removal of the clipping diodes. I am currently looking for an alternative way to stop VAS saturation. An alternative method is (which worked very well but has a quite a few extra parts) detailed in Cordell's book and can be seem in my first amp attempt that turned into a monster.
No problem posting the .asc file. Will do it after work tonight. Would be good having a another brain on this.
Paul
The peaking response was caused by adding the pure capacitive load to test stability. The peaking appears to come from the HEC when driving capacitive loads with no L//R filter. It can be corrected easily but slows the HEC down.
I have not used lag comp on the vas as in Self's book he says that it is a brutal way to treat a VAS. That's why I went for a resistive load back to the IPS output. This seems to reduce the harmonics at the VAS.
The distortion figures can be made much better with the removal of the clipping diodes. I am currently looking for an alternative way to stop VAS saturation. An alternative method is (which worked very well but has a quite a few extra parts) detailed in Cordell's book and can be seem in my first amp attempt that turned into a monster.
No problem posting the .asc file. Will do it after work tonight. Would be good having a another brain on this.
Paul
This is a CFB topology, its quite different to VFB. Self´s view is not of any consequence here youll find. Self actually shows this topology and claims its sub optimal, little does he know that many of the best amps actually use this topology. The way he wrote about it I have doubts in my mind if he is aware of the difference between CFB and VFB, see what he calls it. I doubt youll find a CFB opamp that is not compensated in this way. As the beta enhanced vas has much higher gain it could be of some value here but Id have to look at simulations. Without the beta enhancement I doubt it would be.
I havent got much experience with hawksford error correction, have you tried ONDF error correction, I get better results.
This topology clips simmetrical and cleanly, I wouldnt bother too much with clipping diodes.
A good example of this topology is the british Cyrus amp range, from model 3 upwards about all models use this topology.
I havent got much experience with hawksford error correction, have you tried ONDF error correction, I get better results.
This topology clips simmetrical and cleanly, I wouldnt bother too much with clipping diodes.
A good example of this topology is the british Cyrus amp range, from model 3 upwards about all models use this topology.
Thank you for taking interest in my little project. I am just beginning in the field of amp design and have much to learn.
I had to use some form of clipping protection with this amp as when the VAS saturates the output completely collapses, as you will see when you try simulating my design once I have posted the .asc file.
My main design goals are to have a very stable amp, well behaved into clipping and lastly to have reasonably low distortion.
would you be kind enough to post a link to an example of this ONDF correction? I have done a quick google (Can't use internet too much during work time) and found luxman references??? Or even a link to a schematic of one of your amps?
I will be trying different compensation as you suggest but to the power rails as I would like to keep ground connections to a minimum to make PCB layout easier.
Shame the only Cyrus amp I have access to is a Cyrus 2.
I had to use some form of clipping protection with this amp as when the VAS saturates the output completely collapses, as you will see when you try simulating my design once I have posted the .asc file.
My main design goals are to have a very stable amp, well behaved into clipping and lastly to have reasonably low distortion.
would you be kind enough to post a link to an example of this ONDF correction? I have done a quick google (Can't use internet too much during work time) and found luxman references??? Or even a link to a schematic of one of your amps?
I will be trying different compensation as you suggest but to the power rails as I would like to keep ground connections to a minimum to make PCB layout easier.
Shame the only Cyrus amp I have access to is a Cyrus 2.
This version was a bit of fun.
Check the specs ha ha. Can't take them seriously myself. All I have done is implemented hifisonix AEFC and modified the DC servo slightly.
1KHz +/- 2V = 0.000001%
1KHz +/- 32V = 0.000004%
20Khz +/-2V = 0.000008%
20Khz +/-32V = 0.000213%
THE AEFC has improved the THD by almost an order of magnitude
The only penalty is clipping behaviour.
What do people think? I've broken the rules of CFB, I think.
Edit: obviously this is in the dream world of SPICE.
Check the specs ha ha. Can't take them seriously myself. All I have done is implemented hifisonix AEFC and modified the DC servo slightly.
1KHz +/- 2V = 0.000001%
1KHz +/- 32V = 0.000004%
20Khz +/-2V = 0.000008%
20Khz +/-32V = 0.000213%
THE AEFC has improved the THD by almost an order of magnitude
The only penalty is clipping behaviour.
What do people think? I've broken the rules of CFB, I think.
Edit: obviously this is in the dream world of SPICE.
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I don't see any way to adjust the output stage's bias current. Exicon's datasheet for those output transistors says that their threshold voltage can vary as much as 1.4 volts (see attached snippet), but I can't find a "bias spreader" circuit that allows you adjust the gate-to-source voltage via a trimmer potentiometer. Normally such a circuit would permit the adjustment of the output stage bias current flowing thru, and measured across, R8 + R10.
tl/dr: what if they ship you MOSFETs whose threshold voltage differs from the LTSPICE modeled value? Maybe you might want to simulate at both extremes of the datasheet permitted range, n'cest pas? Four "process corner" sims: Plo_Nlo, Plo_Nhi, Phi_Nlo, Phi_Nhi ??
Edit: for square wave testing you'll want to change C15 to 0.1 pF.
tl/dr: what if they ship you MOSFETs whose threshold voltage differs from the LTSPICE modeled value? Maybe you might want to simulate at both extremes of the datasheet permitted range, n'cest pas? Four "process corner" sims: Plo_Nlo, Plo_Nhi, Phi_Nlo, Phi_Nhi ??
Edit: for square wave testing you'll want to change C15 to 0.1 pF.
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Mark,
I can answer the first question. The bias current is controlled by R34.
I'll have to inspect the models and figure out how to change the threshold voltage. I do have the MOSFETs in my possession so i could measure the threshold voltages. Just scared of ESD damage.
Wouldn't the HEC "correct" the variance in the threshold voltage?
I seem to remember from the semelab application note, that matched mosfets have 0.1R source resistors and unmatched have 0.2R.
Oh yes, forgot about changing C15
Thank you for your help!
Paul
I can answer the first question. The bias current is controlled by R34.
I'll have to inspect the models and figure out how to change the threshold voltage. I do have the MOSFETs in my possession so i could measure the threshold voltages. Just scared of ESD damage.
Wouldn't the HEC "correct" the variance in the threshold voltage?
I seem to remember from the semelab application note, that matched mosfets have 0.1R source resistors and unmatched have 0.2R.
Oh yes, forgot about changing C15
Thank you for your help!
Paul
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One thing I have been considering for a while was an SMD layout for whatever I am going to build. Small signal transistors are no problem but finding driver / pre driver transistors has left me banging my head on the floor. Can't seem to find anything over 1W and getting confused by the datasheets where they spec 1W and then underneath use something like Tc = 25c 10W. I don't understand. (Google hasn't been my friend this time). Need a numpty's guide / explanation please.
(Google hasn't been my friend this time). Need a numpty's guide / explanation please.medium power transistors usually have two different power ratings.
The lower without a heatsink uses the devices Rth j-a as the thermal resistance. This is the typical 1W figure you have seen.
The higher with an infinite (perfect) heatsink uses the devices Rthj-c as the thermal resistance. This is the 10W figure you have seen.
The datasheet usually has a graph showing the temperature de-rating for both configurations where Poperation vs Tc is plotted showing both having ZERO Poperation at Tc=150°C
The lower without a heatsink uses the devices Rth j-a as the thermal resistance. This is the typical 1W figure you have seen.
The higher with an infinite (perfect) heatsink uses the devices Rthj-c as the thermal resistance. This is the 10W figure you have seen.
The datasheet usually has a graph showing the temperature de-rating for both configurations where Poperation vs Tc is plotted showing both having ZERO Poperation at Tc=150°C
Thank you Andrew. So using this plot and then sizing the copper pour area correctly on the PCB I should be able to use some sort of SOT package device instead of TO126 and TO220 devices. I shall have a study during lunch time. SMD has the advantage of not only being smaller it also allows grounding to be better on the 2nd layer.
Let's see if I can understand this... I suspect the SOA plot will come into this as well.
I think if I have this right. You first pick a safe operating temp and use the Poperation - tc plot to determine this using expected power dissipation. Then you linearly de-rate the SOA according to this temp. Then you know what size the copper pour area has to be. Not all datasheets have this Poperation - tc plot so you have to use other data sheets for this or the thermal resistance between the device and the heatsink. Then I thought you could bolt a normal heat sink to this copper area to increase dissipation. Finding suitable medium power SMD devices is not easy. They seem to be going obsolete pretty quickly. Why is everything going to the switching side of things?
Thankfully Mouser and Digikey exist... If it was limited to Farnell and RS I'd be screwed.
Next problem is finding SMD film caps of less than 100pF. Don't really want to use ceramics. But if I do then, am I right in thinking that Cog are the best version?
Thankfully Mouser and Digikey exist... If it was limited to Farnell and RS I'd be screwed.
Next problem is finding SMD film caps of less than 100pF. Don't really want to use ceramics. But if I do then, am I right in thinking that Cog are the best version?
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