Overload recovery etc
Toni, please confirm this is what the 20kHz overload looks like.
If you have a 1930/5171 version still around, please take some pics of 20kHz overload if you ever fire it up again. But don't do it just for this.
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That's why I asked Toni if he has looked at 20kHz overload on the 1930/5171 versions.
I take with a large pinch of salt, sims showing THD below 1ppm but I really want LTspice to show macro behaviour like overload.
When we get Toni's 'real life' results, may I beg some SPICE guru to modify the 1837/4793 & 1930/5171 models so they at least show some resemblance to 'real life' overload on this simple design?
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If I was doing a commercial design, I would be testing with a variety of slight and heavy reactive loads too. But I can't ask Toni to do this as the danger of the load & amp releasing Holy Smoke is quite high.
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Current Mirror stuff
Adjusting the resistors allows you to give both current mirror BJTs (and also the input cascodes) 'equal' Vce. I had this as a tip from Scott Wurcer but it doesn't give any improvement to THD until it approaches 1ppm.
You can only do this with BJTs with good quasi-saturation behaviour like bc560. Thanks for this keantoken
But the mirror doesn't 'drive the VAS into saturation.' Instead it affects how fast it 'drives the VAS OUT of saturation'. For this, the mirror resistors have to be small, ie the mirror needs to sit closer to the rails.
I've been playing with this stuff cos the 'blocking' with 1837/4793_a sims. But these only give small improvements compared to changing to 1930/5171_d on the sims.
This is #274 amp with 3.85Vp i/p at 1kHz and 8R load. 1837/4793_a used in VAS/CCS for this sim There is a small amount of 'blocking' as it comes out of +ve overload but if this was 20kHz, it would be considered 'mild'.
Toni, please confirm this is what the 20kHz overload looks like.
If you have a 1930/5171 version still around, please take some pics of 20kHz overload if you ever fire it up again. But don't do it just for this.
_______________
The 'correct' models are those which result in sims. closest to 'real life'.
That's why I asked Toni if he has looked at 20kHz overload on the 1930/5171 versions.
I take with a large pinch of salt, sims showing THD below 1ppm but I really want LTspice to show macro behaviour like overload.
When we get Toni's 'real life' results, may I beg some SPICE guru to modify the 1837/4793 & 1930/5171 models so they at least show some resemblance to 'real life' overload on this simple design?
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Definitely with 8R attached.
If I was doing a commercial design, I would be testing with a variety of slight and heavy reactive loads too. But I can't ask Toni to do this as the danger of the load & amp releasing Holy Smoke is quite high.
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Current Mirror stuff
Actually they do. The input to the VAS is set by the VAS conditions. But the other side of the current mirror is set by the resistor voltage drops.
Adjusting the resistors allows you to give both current mirror BJTs (and also the input cascodes) 'equal' Vce. I had this as a tip from Scott Wurcer but it doesn't give any improvement to THD until it approaches 1ppm.
You can only do this with BJTs with good quasi-saturation behaviour like bc560. Thanks for this keantoken
The VAS doesn't drive the mirror. It's the other way round.
But the mirror doesn't 'drive the VAS into saturation.' Instead it affects how fast it 'drives the VAS OUT of saturation'. For this, the mirror resistors have to be small, ie the mirror needs to sit closer to the rails.
I've been playing with this stuff cos the 'blocking' with 1837/4793_a sims. But these only give small improvements compared to changing to 1930/5171_d on the sims.
Attachments
Dear kgrlee,
at the end of next week maybe we have some overload pics. Overload testing C5171/A1930 can only be done with the development version which contains only 4 power bjt's instead of 16. So it may be different from 8R full load with current C4793/A1837 test.
Of course I can do a overload test as the current short circuit protection is very simple and can easily be deactivated.
The amp modules have been running many hours with continuous (!) power of 200W@8R using different frequencies so a short time overload just long enough to take some scope photos is really no problem. But will take some days as I am currently very busy.
About power tests: Any good hints to diy build a silent reactive load which withstand > 200W?
BR, Toni
at the end of next week maybe we have some overload pics. Overload testing C5171/A1930 can only be done with the development version which contains only 4 power bjt's instead of 16. So it may be different from 8R full load with current C4793/A1837 test.
Of course I can do a overload test as the current short circuit protection is very simple and can easily be deactivated.
The amp modules have been running many hours with continuous (!) power of 200W@8R using different frequencies so a short time overload just long enough to take some scope photos is really no problem. But will take some days as I am currently very busy.
About power tests: Any good hints to diy build a silent reactive load which withstand > 200W?
BR, Toni
Dear michael,
have done many simulations and the results are always the same:
Using single slope or dual slope limiter always increases distortion factor 10 to 100 times. Can you confirm this, that those type of limiters can decrease sound quality?
Attached some 2 screenshots of dual slope test.
A third picture shows the behaviour of the simple current limiter which shows clearly a DC SOA violation but should withstand 10 - 100ms short circuit situations without any problems. The simple protection is distortion neutral - maybe because there is no reference current flowing from/to rails?
The amplifier pcb will get place holders for different short circuit protection variants so one can decide if best sound quality or best output stage security is desired.
BR, Toni
Attachments
You clearly haven't read the paper I recommended as carefully as you should. For a start you must never have base-collector capacitors across your potection transistors.
Secondly you should have used base ballast resistors for each of your protection transistors. And what possible reason could you advance for using two zeners in series?
I don't know whether your derivation of component values for your protection circuit are correct, and I have no idea what your worst case design load, given your chosen protection locus, is.
You also need resistance between the stage preceeding the protection circuit and the output stage to facilitate the clamping action of the protection transistors.
I don't know whether you calibrated your simulation model of the protection circuit, so I cannot deduce whether your SOA plots are accurate.
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Perhaps we misunderstand each other?
How can altered Current Mirror emitter resistors alter the Vce of the CM transistors, if the LTP current is constant and the mirror is balanced?
Did you mean the Vce of the cascodes? That will be altered, of course.
Best wishes
David
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How do you do the SOA plots in the first screen shot?
Sorry if this is an LTSpice newbie question but I want to sim the distributed driver version that you posted.
Best wishes
David
Dave, the bias voltage of the VAS minus the degeneration voltage determines CM output Vce. Thus increasing degeneration decreases Vce, bringing the transistor closer to quasi-saturation.
Purists would want Vce for the current mirror to be matched, and set degeneration for that goal. My point is only that regardless of matching, the lower Vce, the closer to quasi-saturation and the smaller the collector impedance. CM matching will not do anything to help quasi-saturation, and this is something not many seem to know about.
astx's results went against my original suggestions, so I am not defending myself, just adding to the discussion.
Purists would want Vce for the current mirror to be matched, and set degeneration for that goal. My point is only that regardless of matching, the lower Vce, the closer to quasi-saturation and the smaller the collector impedance. CM matching will not do anything to help quasi-saturation, and this is something not many seem to know about.
astx's results went against my original suggestions, so I am not defending myself, just adding to the discussion.
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Vce of the diode connected BJT in the current mirror is fixed. Regardless of the emitter resistors (within reason) it is ... 1 diode drop.
But the other BJT has a Collector voltage which is FIXED by the VAS operating conditions. Changing the the emitter resistors alters the Emitter voltage. Ergo, changing the emitter resistors will change Vce = Vc - Ve for that transistor..
I haven't done THD tests with & without single/double slope limiting but I HAVE done listening tests.
In the early 80's, many big (& small) amps had single or double slope limiting.
The double slope limiters had a sound which we called 'snap crackle pop' limiting cos that was what it sounded like when triggered. (I was really a speaker & Double Blind Listening Test pseudo guru in my previous life
) This isn't a golden pinnae type observation but something you could induce with the right (evil) speaker and music so anyone could hear it.My present prejudice is to have only simple current limiting like Toni. BJTs are much more rugged than in the 80's so single/double slope limiting is probably unnecessary today.
.. and nearly as cheap to have another pair of output devices.
I understand your point and do address it below. A difference of assumptions has lead to some misconceptions.
I did specify "the mirror is balanced".
What I mean is that the Vce of the VAS connected transistor must match that of the diode connected transistor, which is fixed.
When you alter the CM emitter resistors that means the VAS input potential must also be altered to maintain the balance, so the VAS connected BJT collector potential is not fixed.
With an EF Assisted VAS it is easy to maintain the balance with altered emitter resistors and not alter the VAS quiescent current. Similarly with an EF Assisted Current Mirror.
Less convenient with the simpler circuit. I have seen this done with a diode drop at the input to the VAS.
Best wishes
David
Same chapter at least, but maybe not quite in unison.
Perhaps better to move this to new thread or else Toni may be annoyed.
Best wishes
David
I obviously don't know enough to be able to explain what is happening, but I will try again.
The LTP drives the VAS. The VAS Vbe voltage varies in response to the LTP output.
The CM sees the Vbe variations and changes what it is doing in response to that changing Vbe. i.e. the VAS drives the CM.
The other quotes seem to show that they don't agree with your blanket "it's the other way around".
Worked this out, so no need to respond unless there are some tricks I should know.
Best wishes
David
AndrewT;3505665The CM sees the Vbe variations and changes what it is doing in response to that changing Vbe. i.e. the VAS drives the CM.[/QUOTE said:Er..rh! The current mirror on the LTP helps to provide HiZ output for the IPS. This Holy HiZ is a current source.
If the current mirror is implemented properly (well away from pseudo saturation bla bla this current source is relatively unaffected by what the VAS presents to it as long as the VAS input Z is smaller than the Holy HiZ. ie the current output of the LTP+CM etc is unchanged regardless of what the VAS Vbe is doing.
In a well designed amp of Blameless type, this will always hold.
Of course a badly designed IPS with rotten CM, inappropriate choice of BJTs & operating point, loadsa pseudo saturation bla bla ... will certainly change what it is doing in a manner that compromises the current output of the IPS.
But I seem to have lost the original point of this argument. Why is this important? Are you trying to design a better CM? If so, may I recommend keantoken's pontificating at the start of this thread.
Dear David,
rename file
2stageEF_class_AB_power_amplifier_soa_drv_d2.txt
to
2stageEF_class_AB_power_amplifier_soa_drv_d2.plt
and load it after a simulation of
2stageEF_class_AB_power_amplifier.asc
To add your own SOA curves for a given bjt save a "plt" file and add lines and text. Here an example of the SOA curve of TTC5200/2SC5200 (values are extracted by hand from datasheet).
Line: "A" 3 0 (1,14) (5,14)
Line: "A" 3 0 (5,14) (10,14)
Line: "A" 3 0 (10,14) (14,10)
Line: "A" 3 0 (14,10) (20,7.5)
Line: "A" 3 0 (20,7.5) (30,5)
Line: "A" 3 0 (30,5) (40,3.6)
Line: "A" 3 0 (40,3.6) (50,2.35)
Line: "A" 3 0 (50,2.35) (60,1.4)
Line: "A" 3 0 (60,1.4) (70,0.96)
Line: "A" 3 0 (70,0.96) (80,0.65)
Line: "A" 3 0 (80,0.65) (90,0.46)
Line: "A" 3 0 (90,0.46) (100,0.34)
Line: "A" 3 0 (100,0.34) (200,0.06)
Text: "A" 1 (50,5) ;TTC5200
Text: "A" 1 (50,4) ;DC SOA @ 25 degree
Line coordinates are to be prepared in the form
- (VoltageFrom, AmpereFrom) (VoltageTo, AmpereTo)
The point is that the initial discussion of Current Mirrors in this thread had recommendations that were poor (Keantoken), better but incorrectly explained (manso) or incomplete and not very perceptive (me). So I wanted to clarify this and possibly further improve Toni's amp.
Not wisely
No disrespect to Keantoken, he's too smart not to admit a minor error.
Best wishes
David
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