This is completely untrue.
Simple current limiting makes extremely poor use of the SOA if it's to protect the output devices at all; just read Douglas Self. It's probably the worst false economy in amplifier design. For this reason I didn't even consider it in my paper.
Current Mirrors, Overload & sims
I note keantoken's lack of facility with noise theory but I'm also not sure how manso gets less Loop Gain with more degeneration in the CM unless there is loadsa pseudo-saturation taking place.
My 0.02c is to note that in #4 of tpc-vs-tmc-vs-pure-cherry I increase Self's CM resistors to match Vce but note it only makes a difference cos THD at 20kHz is at 1ppm.[*]
However, I'd be very grateful if Dave can show some simple examples of his ..
[*]On Toni's amp, I'm more concerned with the blocking on +ve overload with the 2sa1837/c4793_a VAS sims. Smaller CM resistors help alleviate this slightly as it is the mirror that pulls the VAS out of saturation.
But we don't have a handle on this as the sim doesn't reflect 'real life'.
Any SPICE guru's want to fudge Andy_C's models to better match 'real life' here?
I've just gone through the thread looking for the above gentlemen's posts on current mirrors.
I note keantoken's lack of facility with noise theory but I'm also not sure how manso gets less Loop Gain with more degeneration in the CM unless there is loadsa pseudo-saturation taking place.
My 0.02c is to note that in #4 of tpc-vs-tmc-vs-pure-cherry I increase Self's CM resistors to match Vce but note it only makes a difference cos THD at 20kHz is at 1ppm.[*]
However, I'd be very grateful if Dave can show some simple examples of his ..
I'm unable to figure out how he do this.
[*]On Toni's amp, I'm more concerned with the blocking on +ve overload with the 2sa1837/c4793_a VAS sims. Smaller CM resistors help alleviate this slightly as it is the mirror that pulls the VAS out of saturation.
But we don't have a handle on this as the sim doesn't reflect 'real life'.
Any SPICE guru's want to fudge Andy_C's models to better match 'real life' here?
Soa sim shows, that it may be impossible to fulfill following statement on page 5 of michael's great soa paper (soaprot_12-03-2012.pdf)
In combination with the bad SOA of 2SC5200 at high voltages and the used emitter resistor of 0.47R it is not possible to get this line so flat that the DC SOA curve is not violated => need to be lower as 1A.
If above statement also has to be fulfilled with dual slope protection then it is impossible to use any other protection circuit as the simple current limiter.
Am I right?
BR, Toni
With this arrangement, it is essential that the linear protection locus intersect the SOA’s Vce axis at a value greater than the sum of the moduli of the amplifier’s voltage supplies; otherwise P1 T turns on under normal loading when the output swings negative, even with the output open-circuit. Similarly, P2 T would be activated under normal output loading when the output swings positive. This effectively short-circuits the “small signal” circuit preceding the output stage directly to the output,
causing gross distortion.
If I correctly understand then the linear protection locus intersect has to be at Vce axis > 142 Volt as this is the sum of amplifiers rail voltages?causing gross distortion.
In combination with the bad SOA of 2SC5200 at high voltages and the used emitter resistor of 0.47R it is not possible to get this line so flat that the DC SOA curve is not violated => need to be lower as 1A.
If above statement also has to be fulfilled with dual slope protection then it is impossible to use any other protection circuit as the simple current limiter.
Am I right?
BR, Toni
Correct. If your output transistors do not permit you to do this, then reduce your supply rail voltages or change the output transistors.
Dear Michael,
thanks for answer. It is now clear why simulation showed 10 to 100 times higher distortion...
I've been thinking more about the CM issue. I didn't take into account all the factors. I will try to make a more complete analysis here.
The main mechanism of distortion caused by a faulty mirror is its output impedance. I'll assume this impedance itself is negligibly nonlinear in reasonable operating conditions, and that it adds distortion by shunting the input of the VAS.
Vce not only modulates collector impedance, but Vbe as well. With 27mV of degeneration, the resulting Ic modulation will be halved. With 27mV*2=54mV degeneration, it will be 1/3, and so on. So IF Vbe modulation divided by Rm is greater than Zcb, degeneration will improve the output impedance of the current mirror. But to apply this we need to know how great the Vbe modulation is.
My Kmultipliers get a PSRR of ~60db with negligible base source impedance, so we can say that for 1V Vce, you get 1mV Vce modulation for the BC550C. For a 33R degenerated VAS at 10mA with a 1mA load, the Vce modulation of a BC550C CM will be ~36.3mV. That means Vbe modulation is ~36.3uV. For a CM at 2mA Ic without degeneration, that means 2.69uA Ic modulation. So 36.3mV/2.96uA=12.2k collector impedance. Like kgrlee says, this will cause distortion if it is not significantly higher than your VAS Zin. A buffered VAS can have very high Zin.
Zce caused by Vbe modulation will be halved by the first 27mV of degeneration. Another 27mV of degeneration and it will be 1/3rd and so on. Eventually, the decrease in Vce will bring a decrease in collector impedance that will cancel out the benefit that degeneration brings. Some transistors will be long past this point in the position of a current mirror.
Noise is another variable. Noise does not affect linearity but does make it hard to appreciate (subtle grin). I'm not an expert but if the noise mechanism is a noise voltage source in series with Vbe, the same rule applies as for Vbe modulation. The first 27mV degeneration will halve it, another 27mV will make it 1/3rd and so on.
The difficulty is that all three of these variables (noise, Vbe, Zcb) are variable and you have to have specific knowledge about the transistor in question. Without this knowledge, the best way to choose degeneration is to measure THD+noise directly and choose the best value.
With the right knowledge we could determine based on astx's results which was the distortion mechanism affecting the current mirror. The BC327-40/337-40 are great at low Vce and not slower than the 5551/5401, and are also supposed to have very low noise. So with broader consideration, they would be my first choice for this current mirror.
The main mechanism of distortion caused by a faulty mirror is its output impedance. I'll assume this impedance itself is negligibly nonlinear in reasonable operating conditions, and that it adds distortion by shunting the input of the VAS.
Vce not only modulates collector impedance, but Vbe as well. With 27mV of degeneration, the resulting Ic modulation will be halved. With 27mV*2=54mV degeneration, it will be 1/3, and so on. So IF Vbe modulation divided by Rm is greater than Zcb, degeneration will improve the output impedance of the current mirror. But to apply this we need to know how great the Vbe modulation is.
My Kmultipliers get a PSRR of ~60db with negligible base source impedance, so we can say that for 1V Vce, you get 1mV Vce modulation for the BC550C. For a 33R degenerated VAS at 10mA with a 1mA load, the Vce modulation of a BC550C CM will be ~36.3mV. That means Vbe modulation is ~36.3uV. For a CM at 2mA Ic without degeneration, that means 2.69uA Ic modulation. So 36.3mV/2.96uA=12.2k collector impedance. Like kgrlee says, this will cause distortion if it is not significantly higher than your VAS Zin. A buffered VAS can have very high Zin.
Zce caused by Vbe modulation will be halved by the first 27mV of degeneration. Another 27mV of degeneration and it will be 1/3rd and so on. Eventually, the decrease in Vce will bring a decrease in collector impedance that will cancel out the benefit that degeneration brings. Some transistors will be long past this point in the position of a current mirror.
Noise is another variable. Noise does not affect linearity but does make it hard to appreciate (subtle grin). I'm not an expert but if the noise mechanism is a noise voltage source in series with Vbe, the same rule applies as for Vbe modulation. The first 27mV degeneration will halve it, another 27mV will make it 1/3rd and so on.
The difficulty is that all three of these variables (noise, Vbe, Zcb) are variable and you have to have specific knowledge about the transistor in question. Without this knowledge, the best way to choose degeneration is to measure THD+noise directly and choose the best value.
With the right knowledge we could determine based on astx's results which was the distortion mechanism affecting the current mirror. The BC327-40/337-40 are great at low Vce and not slower than the 5551/5401, and are also supposed to have very low noise. So with broader consideration, they would be my first choice for this current mirror.
Dear keantoken,
soon I will get my "Distortion Magnifier" Kit (developed by Bob Cordell; search for "pilgham audio") so I am able to get more out of my VP-7723D audio analyzer.
Are Fairchild BC327-40/337-40 types for testing OK?
BR, Toni
There is no eagle file available. If the design works there will be a gerber extended format available for download.
Some thoughts about current limit:
BR Toni
- Power supply is powered by 650VA-700VA / 2x48V Toroid.
- Amplifier's output stage bjt's are simple current limited by 2.4A per device
- Short circuit situation could draw max. 2.4*8 = 19A current.
- Power supply sags very quickly down to a voltage region where 8 2SC5200 can withstand a short circuit period a very long time - more than enough time to blow a fuse or shut down amplifier due to too low rail voltages (e.g. microcontroller sensed shutdown).
BR Toni
Just be careful and do it as quickly as you can.
I used a Switched Capacitance Box as in School Lab experiments to check overload & stability very quickly.
But I had to change some of the Capacitors in the box because their voltage rating wasn't high enough.
Usually (??!) pure capacitance doesn't dissipate any power but very high currents are still possible. I don't test above 1u. The 2uF load used by reviewers in the old days was a leftover from when the QUAD ELS 57 first came out. In fact, it didn't even represent this load.
The worst loads for stability are usually 1 - 10nF pure capacitance but testing with a big guitar speaker at different power levels & frequencies is also instructive.
I've just ...look[ed] for the ... posts on current mirrors.
I note keantoken's lack of facility with noise theory but I'm also not sure how manso gets less Loop Gain with more degeneration in the CM unless there is loadsa pseudo-saturation taking place.
It's all Self's fault! If you don't consciously think about it then it is easy to automatically apply the same rules to the emitter resistors of the Current Mirror pair as to the LTPair. But a clue that they are very different is that the noise decreases as the CM resistor values increase, the complete opposite of the LTP resistors. Similarly with other behaviour. Low values are suboptimal in almost every way. Increased values are quieter and actually improve the quality of the CM. So Self's values seem to have been picked without analysis and then used by others without much reflection.
Hence Keantoken's recommendation of badly low values and my slowness to detect the error in manso's statement that increases would lower gain.
Smart move and demonstrates your independence too
It is not hard to balance the mirror.
For a one transistor VAS the base current of the VAS should equal total base current of the CM transistors So for a specific VAS transistor then the only parameter that is free to alter is the VAS current. Say we assume, for convenient numbers, that the hFE of the VAS transistor is the same as the CM transistor then the VAS current must be twice each individual CM transistor - so the VAS emitter resistor will be just a bit less than half the CM emitter resistors. (there is about 20mV extra Vbe across the VAS because of the doubled current.)
In other words, as the CM resistors increase then so does the VAS emitter resistor to keep the CM transistor Vce constant.
With an EF assisted VAS we can set this condition for the EF transistor with the EF emitter resistor and still have a free parameter in the VAS emitter resistor to set the VAS quiescent current.
It may be better to connect the EF emitter resistor directly to the rail rather than to the VAS emitter as you do.
I know Cherry does it too but I suspect the base current cancellation will be more dependable in the face of power supply variation.
Have not checked this however.
Make sense?
If the mirror is kept balanced as above then the Vce will not decrease, it stays constant as the CM resistors are increased, so it is almost pure benefit. You do lose VAS headroom of course.
JCX also mentioned the benefits of current mirrors on Zcb modulation a while back.
Best wishes
David
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Dear Dave, keantoken,
on simulating this amplifier THD20k@200W@8R lowers e.g. from 0.000894% to 0.000878% if EF resistor is directly connected to the rail.
Not really much but by simply changing a connection we take it if other parameters like PSRR or overload behavior are unaffected.
you mean test it but only for a few milliseconds to avoid crashboombang?
.Simulation shows for 1µF@20kHz@40VRMS a current of 7A peak ...
BR, Toni
Dear Dave, keantoken,
on simulating this amplifier THD20k@200W@8R lowers e.g. from 0.000894% to 0.000878% if EF resistor is directly connected to the rail.
Not really much but by simply changing a connection we take it if other parameters like PSRR or overload behavior are unaffected.
The main benefit is not the reduction in distortion but that it confirms the theory of base current cancellation. So variations like PSRR should be improvements too. Maybe small but, as you say, why not take them if they are free
I should have mentioned that the primary reference for CM noise is A. Bilotti. IEEE Journal of SSCircuits. 1975. and thanks to Samuel for that.
Photos look nice. The boards in that orientation will be thermally asymmetric, probably small but have you evaluated this?
Best wishes
David
I usually try both and use whatever gives best THD. The 2 connections have slightly different distortion profile and in many cases, can provide some cancelling of 2nd.
If I'm bothered about blocking, I connect the VAS enhancer emitter resistor to rail as this gives faster turn off for the VAS
__________
Toni, I had a bad experience with my Switched Capacitance Box because I didn't check the voltage of the caps.
But my Resistive Load was 2 x 10 x 8R 20W metal cased resistors mounted on 1m of Heatsink Extrusion. I could do 2x500W 8R or 1 x 1000W 4R with only a nice warming for my feet in winter
It was built to test a Rotel RB5000 which is the best sounding amp I have ever used.It was used in all our Speaker Double Blind Listening Tests for nearly 2 decades.
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Enormous!
My currently used resitive load consists of 8 x 1R x 50W mounted on a small recycled vintage heatsink as can be seen on a lab picture (post #1). This heatsink is active cooled during long running power tests. Think it's time to upgrade this load to a stronger one so I am able to do also 400W@4R tests.
BR, Toni
The amplifier should be designed for reactive speaker load driving.you mean test it but only for a few milliseconds to avoid crashboombang?
Simulation shows for 1µF@20kHz@40VRMS a current of 7A peak ...
BR, Toni
This is far more stressful than testing inot resistive dummy loads.
If you have a 8ohms capable amplifier, it should easily cope with driving a 4r0 dummy load for at least a few seconds, not a mere few milliseconds.
Similarly a 4ohms capable amplifier should be tested into a 2r0 load for a second or two, long enough to see the scope trace and long enough for the voltage reading on your DMV to settle.
But do this with a near cold heatsink. You are not testing the heatsink, you are testing the amplifier.
BTW,
this test into a half value dummy load automatically ensures that the current capability of the amplifier is at least twice the peak current when delivering maximum power into rated load.
I now test with 2r7 for a 8ohms capable amplifier to prove 3times current capability.
Dear Dave,
What do you exactly mean by thermally asymmetric? Outputstages have been tested hours under 20kHz@200W@8R in both horizontal positions to check influence on bias thermal drift (which in fact is very low from cold to 50 degree).
BR, Toni