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This is a thread to capture my build of an all-bipolar transistor version of the Lazy Cat simple symmetric amplifier (SSA). The thread that inspired this build is here: http://www.diyaudio.com/forums/solid-state/193923-simple-symetrical-amplifier.html
There are a lot of designs and some great ideas on that thread, but I wanted somewhere to capture this specific build and my experiences - I hope they are helpful to others.
I'm planning to build 3 channels; this will be the main amp for my HT system front and centre speakers. I believe this design has the right qualities for the application - low distortion and good damping factor.
The schematic is attached.
Question: there are capacitors C11 and C12 on the output driver stage to prevent parasitic oscillations of the associated complimentary feedback pairs (Q8-Q10 and Q9-Q11). Should these capacitors be connected to the bases of the driver devices before or after the base-stopper resistors ??
EDIT (4 March 2012) SOME USEFUL POSTS LATER IN THIS THREAD
Details of Hagerman Vbe multiplier are in post 22: http://www.diyaudio.com/forums/soli...simple-symmetric-amplifier-2.html#post2722516
The final as-built schematic shown in post 87: http://www.diyaudio.com/forums/soli...simple-symmetric-amplifier-5.html#post2766572
First Sound! post 179: http://www.diyaudio.com/forums/soli...simple-symmetric-amplifier-9.html#post2831179
Photos of Completed modules post 186: http://www.diyaudio.com/forums/soli...imple-symmetric-amplifier-10.html#post2841557
LTSpice file attached in post 226 (any conflict between this and the schematic in post 87, take the as-built one from post 87): http://www.diyaudio.com/forums/soli...imple-symmetric-amplifier-12.html#post2853654
BOM for as-built version shown in post 242: http://www.diyaudio.com/forums/soli...imple-symmetric-amplifier-13.html#post2933346
There are a lot of designs and some great ideas on that thread, but I wanted somewhere to capture this specific build and my experiences - I hope they are helpful to others.
I'm planning to build 3 channels; this will be the main amp for my HT system front and centre speakers. I believe this design has the right qualities for the application - low distortion and good damping factor.
The schematic is attached.
Question: there are capacitors C11 and C12 on the output driver stage to prevent parasitic oscillations of the associated complimentary feedback pairs (Q8-Q10 and Q9-Q11). Should these capacitors be connected to the bases of the driver devices before or after the base-stopper resistors ??
EDIT (4 March 2012) SOME USEFUL POSTS LATER IN THIS THREAD
Details of Hagerman Vbe multiplier are in post 22: http://www.diyaudio.com/forums/soli...simple-symmetric-amplifier-2.html#post2722516
The final as-built schematic shown in post 87: http://www.diyaudio.com/forums/soli...simple-symmetric-amplifier-5.html#post2766572
First Sound! post 179: http://www.diyaudio.com/forums/soli...simple-symmetric-amplifier-9.html#post2831179
Photos of Completed modules post 186: http://www.diyaudio.com/forums/soli...imple-symmetric-amplifier-10.html#post2841557
LTSpice file attached in post 226 (any conflict between this and the schematic in post 87, take the as-built one from post 87): http://www.diyaudio.com/forums/soli...imple-symmetric-amplifier-12.html#post2853654
BOM for as-built version shown in post 242: http://www.diyaudio.com/forums/soli...imple-symmetric-amplifier-13.html#post2933346
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I wasn't planning to use TMC on this SSA amplifier. I don't think it needs it. I feel the primary benefit of TMC is extending the effectiveness of the -ve feedback to higher frequencies for amplifiers weighed down by large Cdom capacitors. I'm hoping that the SSA amplifier will require very little compensation and so no TMC. Of course it probably depends on keeping a tight pcb layout with not so much stray inductances and capacitances.
I dont understand ............
Current flows across R13 then Q3 ( base of Q3 is positive ) then Q2 ( base of Q2 is at zero ) then across R6 ................... then I cant understand ?????? cannot work in class A must be class B using R12 for an input circuit ????????
I am out of buisness ..........................
Current flows across R13 then Q3 ( base of Q3 is positive ) then Q2 ( base of Q2 is at zero ) then across R6 ................... then I cant understand ?????? cannot work in class A must be class B using R12 for an input circuit ????????
I am out of buisness ..........................
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I've drawn my schematic the same way as lazycat, but if you were to go and look at the JLH class A amplifier you'd find it easier to understand - what Lazycat has done is make it symmetrical. Let me try and clarify it a bit.
Q2 is an input device. The current flow through it depends on the voltage across the base-emitter junction. The voltage at the base is the input signal (wrt ground). The voltage at the emitter is a feedback signal from the output (wrt ground). In other words, Q2 is the 'error amplifier' that is both the input device and -ve feedback device. It's a single device instead of the classic Long Tail Pair.
To see how this feedback signal is derived look at how the output is connected back through R12 and then to ground through R4. Together, R12 and R4 form a potential divider, the classic arrangement for -ve feedback. The junction of R12 and R4 is the -ve feedback signal and it's fed to the emitter of Q2 via R6. This R6 provides some additional degeneration (more about this later). So Q2 is a single input device just like the JLH class A amplifier. The output from Q2 is at it's collector. The collector is cascoded by Q3 - strictly this additional device Q3 isn't necessary but it provides some benefits.
So the output from Q2 collector is a varying current flow, via Q3 it flows through R13, which generates a voltage across the base-emitter junction of Q5. Q5 dutifully amplifies the signal and feeds it to the output stage which buffers it, thus providing lots of output current.
This is a symmetrical amplifier and all that I have described above has a mirror image which provides a complementary signal. So, Q1 is a mirror of Q2; they both see the same input signal and the same -ve feedback signal. However, being complementary (n-type and p-type) they have opposite polarity outputs which are later recombined by the voltage amplification stage. Q4 is the cascode for Q1 and is a mirror of Q3. The output from Q1, via Q4, produces a voltage across the base-emitter junction of Q6, which is a mirror of Q5. And Q5 and Q6 form the voltage amplification stage that recombines the two opposite polarity input signals from the input stage to produce an amplified voltage (wrt ground) for the output. The output is biassed into Class AB by the voltage drop across Q7.
Back to R6, and it's partner R5. They add series resistance to the emitters of their respective devices Q2 and Q1. These additional resistances 'swamp' the lower intrinsic emitter resistance of the input devices which vary between devices because of the nature of manufacturing tolerances. This helps ensure that the two input devices, Q1 and Q2 behave more closely in the same way, as they are designed to do here to minimize distortion. Same story for the degeneration resistors R17 and R18 on the voltage amplification stage of Q5 and Q6 - they help with matching the behaviour of the two devices which we want to operate in concert with each other.
I hope this helps?
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hehehe at first glance SSA front-end looks a mess but when one understand the principle it is child's play simple.
Audiofan, here is a real full balanced version of SSA.
Bigun thanks for your SSA explanation. I will follow TGM5 thread and be supportive if asked.
WOW, A CFP triple output stage for you, Bigun? This is a change (and a stability worry).
'Not sure that the output device is the right place to sense temperature for bias compensation, though. Since Self's work, one of the drivers would seem to be the more appropriate and simpler sensing point.
This is a change (and a stability worry).'Not sure that the output device is the right place to sense temperature for bias compensation, though. Since Self's work, one of the drivers would seem to be the more appropriate and simpler sensing point.
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WOW, A CFP triple output stage for you, Bigun?
'Not sure that the output device is the right place to sense temperature for bias compensation, though. Since Self's work, one of the drivers would seem to be the more appropriate and simpler sensing point.
I think for BJTs the triple output has a lot going for it even though it requires the two caps for stability I don't think these caps need be large enough to impact sonics in any way.
I used this output with my TGM3, also with current feedback. It sounds good but I didn't like the dc offset drift and had to install a dc-servo (single transistor dc-servo mind). The symmetrical front end from lazy cat is a nice way to solve this problem I hope - in a way, my TGM5 is a symmetrical TGM3.
http://www.diyaudio.com/forums/solid-state/167369-designing-tgm3-output-triples.html
It's true to say that in a CFP the 'slave' device is under the grip of the driver (or pre-driver in TGM5) so that temperature control of the slave device is now a different prospect. BUT, in TGM5 it is only the driver that is in CFP configuration, the output pair are in the standard EF configuration and so they need temperature compensation.
One thing I am going to do differently is run the drivers at lower current. In my TGM3 I ran the drivers in high current, like Roender. But in TGM4 I don't want to dissipate so much standing current and although technically not as good, I believe it will be more than adequate for the task at hand. The standing current through the drivers will still be in-line with 'conventional' practice and yet still have the benefits of a triple in terms of isolating the VAS from the non-linear Class AB switching output stage.
I will follow TGM5 thread and be supportive if asked.
thank you !
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I will re-use the old 'TGM' chasis and install a new heatsink recovered from an Onkyo amplifier.
The heatsink has to fit 3 channels which means each amplifier channel has to fit on a 3" x 3" board. I'll be etching them at home, and I want the parts on the top side so that the backside can be a continuous ground plane.
For mechanical stability, power devices will be flat against the underside of the pcb with mounting holes at opposite sides and mid way between top and bottom edges. The general idea is shown in the attachment, with a few surface-mount capacitors thrown in. I have the caps already.
The heatsink has to fit 3 channels which means each amplifier channel has to fit on a 3" x 3" board. I'll be etching them at home, and I want the parts on the top side so that the backside can be a continuous ground plane.
For mechanical stability, power devices will be flat against the underside of the pcb with mounting holes at opposite sides and mid way between top and bottom edges. The general idea is shown in the attachment, with a few surface-mount capacitors thrown in. I have the caps already.
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I have identified a concern with this design that I need to work through - bias stability.
Consider the case with NO input signal, just d.c. conditions.
The current through the output devices depends on the voltage drop across the Vbe multiplier, which depends on the current flow through the VAS. The current flow through the VAS depends on the current flow through the input stage and it's quite sensitive.
The current flow through the input stage depends which depends on the voltage across the base-emitter of the input devices. The input is referenced to ground and is well behaved (we can use an input capacitor if reqd.). The voltage on the emitter of Q1 is set by the potential divider of R7 and R3 in parallel with the current flowing through the input device. The feedback resistor R11 is of no consequence because the output is at zero volts. The voltage divider is stable if the voltage set by the zener diode is stable. I'm happy to accept that this is the case.
However, the current flow through the input stage also depends on the temperature. As the device warms up the base-emitter voltage needed to generate a certain current flow decreases. Since the base-emitter voltage is well controlled, the current flow will increase with temperature.
In my simulations this effect produces enough change in the bias current of the output pair to make this design poor. Had I adopted a lateral FET output I may have gotten away with this variation, but for an all-BJT design the impact on distortion isn't acceptable.
Consider the case with NO input signal, just d.c. conditions.
The current through the output devices depends on the voltage drop across the Vbe multiplier, which depends on the current flow through the VAS. The current flow through the VAS depends on the current flow through the input stage and it's quite sensitive.
The current flow through the input stage depends which depends on the voltage across the base-emitter of the input devices. The input is referenced to ground and is well behaved (we can use an input capacitor if reqd.). The voltage on the emitter of Q1 is set by the potential divider of R7 and R3 in parallel with the current flowing through the input device. The feedback resistor R11 is of no consequence because the output is at zero volts. The voltage divider is stable if the voltage set by the zener diode is stable. I'm happy to accept that this is the case.
However, the current flow through the input stage also depends on the temperature. As the device warms up the base-emitter voltage needed to generate a certain current flow decreases. Since the base-emitter voltage is well controlled, the current flow will increase with temperature.
In my simulations this effect produces enough change in the bias current of the output pair to make this design poor. Had I adopted a lateral FET output I may have gotten away with this variation, but for an all-BJT design the impact on distortion isn't acceptable.
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Few thoughts regarding thermal conditions.
In all amps there is the same story: latent temperature dependency at each stage from input to output. To prevent any damage, in our calculations we have to provide controlled transition from cold off-state to power-on temperature stability conditions, so called warm-up transition phase.
Normally each transistor goes up from room temperature to working conditions temperature. We can play with calculations to suit each separate transistor the most and that at the end it works at optimal physical parameters.
Thermall dissipation deviation percentage from bias conditions to maximum loading program should be very low at all stages except at the output stage. So that puts us to position to regulate only that temperature dependency to protect outputs from thermal break-down all other stages must be independantly fixed to their optimum bias values.
Input stage, from where all begins, will allways tend to change electrical parameters related to temperature, that is why we fix the bias currents and voltage potentials as much as possible to hold it in position. SSA input stage provides very good thermal dependency rejection as long as input BJT pair is thermally coupled.
Vbe multiplier has two major tasks to provide: it is there not only to sense the temperature from the output stage but also acts like a zener so the front-end bias variations have no influence to output bias conditions.
Some more will follow ...
In all amps there is the same story: latent temperature dependency at each stage from input to output. To prevent any damage, in our calculations we have to provide controlled transition from cold off-state to power-on temperature stability conditions, so called warm-up transition phase.
Normally each transistor goes up from room temperature to working conditions temperature. We can play with calculations to suit each separate transistor the most and that at the end it works at optimal physical parameters.
Thermall dissipation deviation percentage from bias conditions to maximum loading program should be very low at all stages except at the output stage. So that puts us to position to regulate only that temperature dependency to protect outputs from thermal break-down all other stages must be independantly fixed to their optimum bias values.
Input stage, from where all begins, will allways tend to change electrical parameters related to temperature, that is why we fix the bias currents and voltage potentials as much as possible to hold it in position. SSA input stage provides very good thermal dependency rejection as long as input BJT pair is thermally coupled.
Vbe multiplier has two major tasks to provide: it is there not only to sense the temperature from the output stage but also acts like a zener so the front-end bias variations have no influence to output bias conditions.
Some more will follow ...
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I'm comfortable with the Vbe multiplier doing it's job regarding tracking temperature of output devices. It's the input stage that I'm less certain of.
In my simulations I'm seeing a microscopic change in current with temperature of the input device - say 10uA/degC. But through the VAS etc. this translates into 3mV/degC across the emitter resistor of each output device. A 5 degC change will shift the bias by 15mV, which is quite a lot given that the idle bias should be 26mV. Maybe this is OK ?
In my simulations I'm seeing a microscopic change in current with temperature of the input device - say 10uA/degC. But through the VAS etc. this translates into 3mV/degC across the emitter resistor of each output device. A 5 degC change will shift the bias by 15mV, which is quite a lot given that the idle bias should be 26mV. Maybe this is OK ?
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I ran the same simulation on my earlier TGM amplifiers with standard LTP input stages. The output bias stability with respect to temperature is 10x better than the SSA. I also looked at Shaan's front end with the diodes between bases of input devices - it's about the same as SSA.
Perhaps this is nothing to worry about.
I've drawn up first draft of pcb design.
Perhaps this is nothing to worry about.
I've drawn up first draft of pcb design.
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So the temperature change from 25°C to 30°C will cause output quiescent current change from 120mA to 190mA. Quite unreasonable sim you have.
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Im glad you found a solution, can you share it? Nico also used two serial 1N4007 diodes to stabilize mid bridge DC level.
BTW I like your SMD PCB very much, especially placement of the outputs, only a GND loop can be a potential interference generator.
I advice you to sim your Vbe multiplier, Vce change vs. Ic and plot the deviation. For Ic use real values plus variation in accordance to temp.
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