If you were to use them in the sub-threshold region, bear in mind that the subthreshold slope for vertical MOSFETs is between 200 and 400mV per decade, whereas it is about 60mV per decade for BJTs.
Cheers,
Bob
Such a cap has little to nothing to do with stabilizing the triple, but with compensating the Miller loop which, in particular if a beta enhancer is used, may have stability issues. If you disagree, I would be happy to listen to any proof you may have. I am in particular curious how do you analyze the triple stability and estimate the stability margins.
Even so, simply a shunt cap is an unnecessary brutal Miller loop compensation method; a lead lag network (that is, a RC series) will save precious loop gain, while providing a very similar stability margin.
Hi Mike,
The shunt cap or Zobel can actually help both Miller loop stability and Triple stability, depending on the particular design and transistor ft involved. I agree, I prefer an RC for the job, and it does not need to be too heavy to help. In some situations, Triples can be difficult to stabilize even with a one-transistor VAS.
One thing I have found useful in evaluating the stability of Triples and other output stages stand-alone is to feed them from a 100 ohm source and look at the frequency response for peaking or other bad behavior. Looking at them with a variety of source impedances from zero to 1k or so can tell a lot. I've also played with such source impedances with a cap or Zobel shunt added. Also with cap loads on the outputs of those output stages. These ad-hoc approaches do not yield a number for phase and gain margin of the Triple, but provide some good insight as to what is going on. Looking at this with different transistor ft can also provide insight.
In connection with this, it is also useful to evaluate the output impedance of the Miller-compensated VAS as a function of frequency. This is easily done by driving a small-signal ac current into the output node of the VAS and looking at the resulting voltage frequency response. In many cases this will reveal rising compensated VAS output impedance in the MHz range, sometimes with peaks - potentially signaling VAS local loop instability.
Cheers,
Bob
Hi Waly,
See my comment above and try some simulations of the type I described. You'll see the role played by source impedance in the Triple especially.
Cheers,
Bob
Hi Mr. Cordell
So the Miller cap is like in your book from the collector of the VAS stage back to it's base. This serve as the capacitor loading of the high output impedance of the IPS to create the dominant pole.
The shunt capacitance is at the collector of the VAS transistor to ground. This cap is actually in parallel with the input capacitance of the pre-driver stage of the OPS?
Isn't that creating a second pole? I though we try to work very hard to make it a dominant pole system so we have one pole cross over. The idea is to make the frequency response from VAS to OPS to beyond 100KHz, keep the output impedance very low so the pole of any capacitance loading the output is beyond 100KHz. Then a zobo (lead lag network) network to keep the loading impedance low to keep the open loop gain from being too high at high frequency.
I understand you said the shunt is a RC lead lag network that you create a pole at low frequency and then kick in the zero at high frequency to give a little phase margin at high frequency. Are you trying to keep the open loop gain at low audio frequency very high, then roll off at -40dB per dec until the zero of the shunt network kicks in and the roll off is back to -20dB per dec?
Thanks
Hi Bob
I put some source resistance in an OPS test simulation once, without much premeditation, and was surprised at the effect.
In particular there was some "excess phase", as strictly defined, in excess of minimum phase.
I was surprised because it is usually considered that excess phase is irrelevant in audio amps, but here it was.
So I simulated more systematically, then noticed you had already shown this on p. 205 in the picture at the bottom and explicitly in the text, even as low as a couple of MHz, sufficiently close to ULGF to effect stability.
Do you have any comments on excess phase in Emitter Followers?
Stability in EF is remarkably non-obvious!
I have read Dennis Feucht's comments on the subject and my tests were very educational but I would like to learn more.
Middlebrook covers this a bit too but I am not sure about his transistor model.
My results so far are consistent with yours and do not accord with Waly, source impedance reduced stability, under typical conditions.
Best wishes
David
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Now you three are confusing me.
Which of the above numbers apply to BJTs and which to FETs?
Here are some 'real life' tests on a plain EF.
Though not of EVIL triples, they support Waly rather than Cordell & Zan.
stability-analysis-ef-output-stages
I can pontificate on the effect of distortion too.
'Pure Cherry' comp. increases the source resistance seen by the O/P stage.
If purely current driven, the Class B stage distortion changes from 'notch' type xover with very high order products ... to a 'single' change of slope.
'Pure Cherry' is also accompanied by a huge amount of Loop Gain around the output stage so the nett result is a reduction in THD ... particularly high order products .. all obtained by driving the O/P stage with HiZ.
Various caveats about competent design of 'Pure Cherry' apply
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I've always had similar results. To ensure stability of an output stage, you have to insert some series resistance in the bases (or gates) somewhere. I mostly have experience with Douglas Self's method, resistors in series with the bases of the driver transistors of a double EF or CFP. The larger the resistor, the better the stability, but the more speed and effective gm you lose.
I start with about 100 ohms and go up from there, checking for parasitics on a heavy inductive load.
Output stage layout is a factor, in so far as the finite speed of the transistors causes inductance in the emitter to be transformed into negative resistance at the base. You need to minimise the inductance of the loop composed of emitters, Zobel network, ground, rail decoupling caps and collectors.
I start with about 100 ohms and go up from there, checking for parasitics on a heavy inductive load.
Output stage layout is a factor, in so far as the finite speed of the transistors causes inductance in the emitter to be transformed into negative resistance at the base. You need to minimise the inductance of the loop composed of emitters, Zobel network, ground, rail decoupling caps and collectors.
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Thank you for that, I should have been clearer that my simulations were about the outer loop stability of a complete amp rather than a local loop in an isolated OPS.
Quite probable that the increased outer loop stability comes at the cost of decreased local loop stability, in this case the EF loop itself.
What are your ideas on how to analyse the EF loop?
Have you looked at Middlebrook's or Feucht's work on this?
Best wishes
David
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Hi David,
Your observations are correct. The input impedance of a Triple EF can be pretty wonky and non-intuitive. This is an example of why SPICE plays an important role in amplifier design, as imperfect as it is.
We know that the input impedance of a resistively-loaded single EF looks capacitive above f-beta of the transistor. We also know that if we capacitively load the EF, the input impedance wraps around another 90 degrees and looks like a negative resistance. Now consider three such stages all in tandem. The complexity if the input impedance can become bewildering, at least to ordinary folks like me.
I have even found that the 4EF quad can actually be more stable than a Triple at times. Go figure. Maybe it has to do with the pre-driver giving the subsequent Triple a lower, better-controlled source impedance.
We must never forget that the current gain of all of these devices is very finite at frequencies above f-beta, and these become very real. Consider 10MHz, where a lot of this bad stuff can be going on. A 10MHz output transistor has a beta of unity. A 50MHz driver has a beta of 5. A 100MHz pre-driver has a beta of only 10. Not pretty. One can argue that higher-ft transistors can be used, but the picture is still pretty bad. BTW, ft droop at high current can make things worse.
Cheers,
Bob
Mine applies to MOSFETs, Waly's applies to BJTs, and Keantoken's applies to both.
Cheers,
Bob
Here are some 'real life' tests on a plain EF.
Though not of EVIL triples, they support Waly rather than Cordell & Zan.
stability-analysis-ef-output-stages
I can pontificate on the effect of distortion too.
'Pure Cherry' comp. increases the source resistance seen by the O/P stage.
If purely current driven, the Class B stage distortion changes from 'notch' type xover with very high order products ... to a 'single' change of slope.
'Pure Cherry' is also accompanied by a huge amount of Loop Gain around the output stage so the nett result is a reduction in THD ... particularly high order products .. all obtained by driving the O/P stage with HiZ.
Various caveats about competent design of 'Pure Cherry' apply
Sorry to disagree. There is nothing in the post that you referenced that reasonably can be extrapolated to support either Waly's or my position. In Jurassic times you didn't simulate, so you largely did not have a clue as to what was going on, especially with something like a Triple.
Cheers,
Bob
Hi Bob,
Sorry for a basic question. Wondering how this would apply to something like the output stage that you show for driving MOSFETs in your book with the CCSs + inverted driver transistors? Does the inverted driver setup handle reactive loads any differently if we assume the OPS is BJT and not MOSFET? Unfortunately, not got the book to hand to give figure reference.
All these little details in amp design can sometimes be a little bewildering...
Many thanks,
Paul
Hi scopeboy,
Yes, base stoppers often help, and of course especially in the output stage. I also discussed in my book the use of base stoppers in the driver. I don't recall Self saying anything about that up to and including his 5th edition, but maybe it is in his 6th edition, published 3 years after my book. But I could be wrong, I could have missed it and it might just be a matter of "great minds think alike".
However, I have found that the use of base stoppers in the driver does not always make things better. The whole thing can be pretty tricky. There is little debate, however, about the use of base stoppers on the output transistors, especially when they are paralleled.
Some folks, including some well-respected designers, go too far with output transistor base stoppers, not realizing that they can seriously compromise bias stability. This is especially the case where they use a low value of RE, like 0.1 ohm or 0.15 ohm. A 10-ohm base stopper is too much.
In some cases, these folks may be resorting to large base stoppers to help local output stage stability in the case where they want to drive capacitive loads without a series inductor L-R network.
Cheers,
Bob
Thanks for the prompt reply, this is pretty much as I understand it and as explained by Dennis Feucht too.
What I don't yet understand is where the excess phase comes from.
In your explanation I don't see any reason for the response to have excess phase, have I missed some point?
Best wishes
David
Self doesn't actually say a word about it, but all of his example circuits and published designs use double EF or CFP output stages, with stopper resistors only in the driver transistor bases and none on the output devices. I think the topics that Doug Self avoids mentioning in his book are just as interesting as the ones that he does cover.
I built my first hifi amp before reading Self's book, and wished I had seen it beforehand. I built my second one before reading yours, and wished I had seen that beforehand too. I guess I need to do a third one now
Wrong guess.
I have no idea how to simulate this to get anything relevant for this discussion. Simulating a triple fed from a 100ohm to 1k source impedance doesn't seem even remotely similar with a triple fed by a VAS with a shunt or lead-lag Miller loop compensation. I also fail to understand how the triple stability can be estimated by peaking in the frequency response, and what exactly means "other bad behavior". By the same logic, two pole compensation is bad, because the frequency response is indeed peaking.
The only way that I know to consistently simulate an EF (single, double, triple) is to use prof. Middlebrook method. Based on this, syn08 calculated some closed form exact and approximate formulas (see the schematics on that page), very handy for simulations in LTspice or other standard simulators. I've used those, and I am unable to confirm that a shunt cap or RC network at the single, double or triple EF input has any impact on the stability. I need to see clear results to believe anything else, knowledge based on hand waving and trust "because I say so" doesn't work for me. If anybody cares, I could show my results here.
Nope, mosfets have a theoretical 60mV/decade subthreshold slope. If some other big fat academic reference is not handy, a simple incursion in Wikipedia will reveal this fact.
I don't recall BJTs having anything remotely similar to subthreshold conduction. Their Ic-Vbe slope is mkT/q where m is a constant and kT/q=26mV at room temperature. In a typical BJT, this stays valid for 10 decades of current or even more.
Hi Paul,
The inverted driver, which I affectionately call a folded emitter follower, is analogous to the first transistor of a diamond buffer. I used the folded emitter follower in the 125w MOSFET amplifiers that I used in my Athena active 3.5-way loudspeakers. I think there is a powerpoint presentation on my website that discusses this aspect of the Athena loudspeakers.
The folded emitter follower driver is synergistic with a MOSFET output stage because of the lower need for MOSFET gate drive current than for base drive of a BJT output transistor. It also naturally limits the current driven into the gate or gate protection diodes of the MOSFET. The collectors of the folded emitter followers can also be bootstrapped to the output node to reduce their needed operating voltage and dissipation, and reduce the effect of their Ccb. For such bootstrapping, local HF stability must be considered.
The folded emitter follower really makes no difference in driving reactive loads under non-overload conditions.
Cheers,
Bob