Do you have any comments on a design like this?
An externally hosted image should be here but it was not working when we last tested it.
Ok, thanks for confirming my doubts. It worked when I first simulated it but after reading your comments I tried doubling the supply voltage and the quiescent current through the output transistors increased from ~70mA to ~700mA.
I modified the circuit to this:
There should be no further problems with this modified circuit right?
I modified the circuit to this:
An externally hosted image should be here but it was not working when we last tested it.
There should be no further problems with this modified circuit right?
) then I source the closest/best compromise mostly from farnell.
I also think it is a good idea to use no higher than the E24 series. Even if you can get more precise values now, you might have trouble in the future, or it might make it harder if someone else wants to replicate your design.
While E24 is good, E12 is better, especially for values <10R or >1M, which can be hard to find or expensive in better than E12.
P.S. There are ways of using current mirrors in symmetrical designs. For instance current feedback, or drawing a a fixed current through a resistor connected to the VAS input.
While E24 is good, E12 is better, especially for values <10R or >1M, which can be hard to find or expensive in better than E12.
P.S. There are ways of using current mirrors in symmetrical designs. For instance current feedback, or drawing a a fixed current through a resistor connected to the VAS input.
So maybe you can't flip a current mirror and let drive voltage into
the next stage go entirely undefined... I can buy that.
But if you let one side of your differential pairs define the voltage
into the next stage, the other side of the differential can still pull
useful (if undefined) opposing current... And you are then holding
both collectors within 0.66V of the same voltage, if that matters.
My stage is a little different, its only the differential flip thing I'm
trying to illustrate for comparison... Q7 Q8 in this drawing....
the next stage go entirely undefined... I can buy that.
But if you let one side of your differential pairs define the voltage
into the next stage, the other side of the differential can still pull
useful (if undefined) opposing current... And you are then holding
both collectors within 0.66V of the same voltage, if that matters.
My stage is a little different, its only the differential flip thing I'm
trying to illustrate for comparison... Q7 Q8 in this drawing....
Attachments
post12.
you have changed the quiescent currents in the EF and the VAS.
Why?
I like the reduction in the collector load resistor value.
But you need a split resistor in the emitter of the VAS.
The outer resistor sets the trigger current for the protection.
The total of the outer and inner resistor sets the VAS quiescent current.
you have changed the quiescent currents in the EF and the VAS.
Why?
I like the reduction in the collector load resistor value.
But you need a split resistor in the emitter of the VAS.
The outer resistor sets the trigger current for the protection.
The total of the outer and inner resistor sets the VAS quiescent current.
To Andrew,
The 68R->10R change in emitter resistance in the VAS (to limit the VAS current to ~60mA) increased the VAS quiescent current so I lowered the collector resistors to compensate. I found that it simulated pretty good with the new ~30mA VAS quiescent current. Don't remember if I also changed the EF quiescent current? I keep changing values all the time and forget alot...
Didn't think of that I could split the VAS emitter resistance.
So I did some further changes, updates in post 12 (running low on space on my webpage so I'm not going to keep older versions).
To all,
The added current mirrors in post 4 increased the bandwidth somewhat so I'll probably include them.
When simulating open loop gain i get (no LP on input):
Post12: f180 = 6.4 MHz (where gain switches sign)
Post4: f180 = 6.0 MHz (where gain switches sign)
The 68R->10R change in emitter resistance in the VAS (to limit the VAS current to ~60mA) increased the VAS quiescent current so I lowered the collector resistors to compensate. I found that it simulated pretty good with the new ~30mA VAS quiescent current. Don't remember if I also changed the EF quiescent current? I keep changing values all the time and forget alot...
Didn't think of that I could split the VAS emitter resistance.
So I did some further changes, updates in post 12 (running low on space on my webpage so I'm not going to keep older versions).
To all,
The added current mirrors in post 4 increased the bandwidth somewhat so I'll probably include them.
When simulating open loop gain i get (no LP on input):
Post12: f180 = 6.4 MHz (where gain switches sign)
Post4: f180 = 6.0 MHz (where gain switches sign)
I don't think the current mirror on the LTP collectors will be effective with the parallel 680r load.
Without the 680r the circuit does not work.
Without the current mirror the circuit does work, but badly.
what is the VAS quiescent current?
Let's call it XmA.
The minimum VAS current is zero mA.
If the signal is symmetrical then the maximum VAS current is 2XmA.
i.e. VAS current = XmA +-<=XmA
The protection transistor must not alter the VAS amplifying characteristics over this whole range. There is an argument that the VAS should be allowed to vary from 0mA to ~3XmA to account for non symmetric signals.
The protection transistor starts to turn on ~400mVbe.
The voltage across the outer resistor of the split emitter resistor must be <~400mV when maximum peak VAS current is passing. Otherwise the protection becomes audible.
Some will argue that adding the protection transistor is audible anyway even when Vbe<<400mV, but that is a different story from deliberate or accidental triggering of the protection when valid audio signals are passing into valid audio loading.
recalculate the two 10r to set the VAS quiescent current and what the outer resistor must be to pass~3XmA for a 400mV voltage drop.
Without the 680r the circuit does not work.
Without the current mirror the circuit does work, but badly.
what is the VAS quiescent current?
Let's call it XmA.
The minimum VAS current is zero mA.
If the signal is symmetrical then the maximum VAS current is 2XmA.
i.e. VAS current = XmA +-<=XmA
The protection transistor must not alter the VAS amplifying characteristics over this whole range. There is an argument that the VAS should be allowed to vary from 0mA to ~3XmA to account for non symmetric signals.
The protection transistor starts to turn on ~400mVbe.
The voltage across the outer resistor of the split emitter resistor must be <~400mV when maximum peak VAS current is passing. Otherwise the protection becomes audible.
Some will argue that adding the protection transistor is audible anyway even when Vbe<<400mV, but that is a different story from deliberate or accidental triggering of the protection when valid audio signals are passing into valid audio loading.
recalculate the two 10r to set the VAS quiescent current and what the outer resistor must be to pass~3XmA for a 400mV voltage drop.
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