My Bridge Amp

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Hi

Lately I've been working on a new circuit topology that I haven't played with before, and have obtained some initial waveforms. Capacitive loading seems thus far a little bit troublesome, but I think the problem lies somewhere within the output section. Just a quick description of the project, this is a bridge amp, with +/- 25V(minus some sag) supply for the output mosfet's. Output goal is 100WRMS into 8Ohm. I have not built an amp before that is half worth a hill of beans with hexfet's, but this one may be promising. The front end, VAS, and drivers use +/- 40V @~35mA regulated. The output transistors used here are 2 pair of these, not quite so complementary, El-Cheap-O Q-fet or hexfet's from Fairchild: http://www.fairchildsemi.com/ds/FQ/FQP16N15.pdf, and http://www.fairchildsemi.com/ds/SF/SFP9540.pdf
The N-ch I have is the 14A version that has apparently been discontinued:rolleyes::whazzat: It has a Rds-on of 0.21 Ohms and the input capacitance is slightly lower. The like polarities don't match well either, apparently, but that doesn't matter in this circuit because they are not parallel, but bridged.
Just for the fun of it, this circuit is constructed completely from discrete components, including the regulator circuit.:) I am ashamed to admit, but there is one capacitor in the signal path:whazzat:, the 1uF polypropylene input cap. There is a lot of feedback but NONE of it is global.:D DC is set via a DC servo circuit that does have to sense the output, but that doesn't count.:p The VAS is a cascode differential balanced bridge, with a closed loop gain of 6.2. The +/- inputs are driven by two "gain cell" circuits, that have a CL gain of 6, so the circuit has an overall Av of about 37 and does not require a balanced line input but rather asymetric. The waveforms shown is the output of both phases which are bridged across the load, both outputs maintain less than 25mVDC from GND, and 10mVDC from each other. This has been an interesting journey so far into new frontiers for me, but it still requires a bit of tweaking, mostly with the output stage circuit....there is still a tiny oscillation of like 5mV at 30 some odd MHz... :dodgy:
 

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Here is some more, there may be a little phase shift at 15Hz, but seems to be a little better at 20Hz. Maybe something else to tweak. It's not too bad though. I don't know what can be tested with a triangle wave, but it sure looks pretty:D. BTW, this is all with the output fet's bias at around 75mA, I think maybe it should be higher. The temp-co seems to be a little be overcompensated too because it starts out at over 100mA until it is warm, then decreases.
 

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Workhorse said:
Where is so-called schematic of your bridge upon the river amp??


Well, there is two places that it exists at this moment. One is between my ears, and the other is sketched out on a poster paper stuck on the wall because it contains 146 transistors and it is the only way I can draw it all out and still see and read the whole thing.:bigeyes: Not sure if I can take a photo of it, maybe a few photos and photshop it.:rolleyes: he he, I doubt if anyone here would want to copy it anyway. To take a general quote from the forum, "that's just too damn many transistors."


:smash:
 
Yeah WHHeww!

I missed a couple when I was counting, there is actually 148 transistors.:xeye: All of them are SOT-23 except 14, 4 outputs (TO-220), 4 drivers (TO-126), 4 Vbe X'ers (TO-126), and 2 TO-92 devices as the pass transistors on the regulator circuit. Otherwise a mix of J-fet and BJT. Many of the BJT's could be condensed into available SOT-563 pakages if a proper PCB were made.:magnify::)
 
After some sleep, I got around to sketching a block diagram of the amp. I took a more 'modular' approach to the design, each circuit performing a general function. With no GNF, this made it easier to construct because I could focus on one circuit network at a time until I get it working properly, then move to the next one, ect. Eventually I was able to exterminate most of the bugs and get all the circuits to work together. Most of my surprise comes as I haven’t yet blown any of the output fets building this circuit. I'm usually par for roasting at least a couple of output pairs experimenting with new circuitry.:hot::flame: :smash:

To input a disproportional signal to the +in of the first gain cell circuit and the -in of the second, a balanced drive can be created for the VAS circuit using two equal gain cell circuits.

Now if I can only get rid of this damned MHz oscillation. I'll try larger gate resistors on the output fets and see if that stops it. Trial and error I suppose....:dodgy:
 

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Here is the 'gain cell' circuit I used. It is self bias using common mode feedback. The transistors labeled 1/2 & 2/2 could be arrays or any general device, I guess. The transistors labeled 1/4 - 4/4 is a THAT 340 matched array. http://www.thatcorp.com/datashts/300data.pdf
I like these, IMO they work quite well, despite only an Hfe of around 100 or so. But high gain is not their intent here. The 5460 has a Vgs of about 2.2V @100uA. 5089 is a low noise, high gain transistor. http://www.fairchildsemi.com/ds/MM/MMBT5089.pdf I have found that, at least for the KSK595's I have, they work great in the 7-10 Vds and 25-50 uA range. I measured Vgs @ 25uA of about -0.35V and Rds of 1500 Ohms. It appears Fairchild MAY have discontinued these, they were 4 cents a piece when I bought them, now they are more than 50 cents and Fairchild appears to be out of stock:headbash:. Seems to be a common trend with them. That's OK, I have about 300 of them.:) I would be willing to bet the circuit could work with just about whatever devices are out there, just adjust the resistor values appropriately. The 4091 is like a J111 and has a Vgs @ 25-50uA of around 9V. The ones I have measure Rds of 22 Ohms, and Vp around -11-12V. The Vgs of the J201 I have @ 50uA is about -0.8V. The output from this circuit drives one side of the complementary input J-fet diff of the VAS. My experience with this method of CMRR has been good, the VAS circuit uses this concept as well. I maybe drifting out in the audiophile high seas of absurdness, but I have had interesting and good enough results to not abandon the concept yet. Much to the contrary. Another positive result of this circuit is it limits current which is always a good thing when building solid state circuits, especially since those THAT chips cost like $8 a piece.:smash:
Don't suppose anyone else has tried anything like this, eh?
 

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Hi Kanwar

I will work it onto a PC drawing eventually.
You are using balanced drive for your floating bridge amp...

There are two of these circuits, the other has the input fed to it's -in node via a voltage divider. The result is an equal balanced signal. These two signals drive the complementary input J-fet's for the VAS section. A floating bridge amp:D...hope it doesn't float away!:clown: The CM feedback loop appears to anchor it well. I have never seen the bias drift. The only trim pots are in the output stages to set their bias. Also the active CMFB bias is not affected by operating temperature. Since the AC doesn't appear to be affected by this bias scheme, I haven't found a reason yet to abandon this idea. Is there a clear reason why this shouldn’t work?

BTW: I have made balanced grounded bridge single supply amp with all N-fets.....

I bet it has less transistors than mine.:p When you say grounded, you mean the bridge input is referenced to one side common since it is single supply or is it floating?
 
Interesting... kinda like one of those grounded collector amps. Mine is not that way, it has two seperate output stages that are the exact same circuit, both are complementary hexfet followers, with EC. From the results of this latest project, I don't think I will ever make an amp with GNFB again. Multiple stages and local feedback is better....IMHO.:D Not sure if I can post a readable schematic, I plan to draw it all on the computer only one time, in Eagle. There is a lot of components so it won't be as easy to follow as the sketch. Maybe I could try to scan it.:rolleyes: If it is readable, I will post it.
Anyway, I finally got around to doing a few cap tests....
 

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BTW both output's are shown in each pic, 10V/Div. The two are added across the load. It is still a little ugly with significant capacitive loading, but the latest tweeks have made it a little better....:dodgy:

So it is moderately stable and fairly fast. Hmmm, now if I only had some real testing equipment. :$: :$: :$: :$:
 

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Hi Kanwar

Now that's an idea that very few on this forum seem to like much. I couldn't agree with you more. It's the way to go about it, IMO. Also you may not need an output coil since there is no GNF loop to corrupt by the components of a nasty reactive load.

THIS circuit has no output coil. There are no zeners in this circuit except for mosfet Vgs protection. I don't like zeners.:yuck: This is the best resolution I can get because of the 100K resolution block in the forum. At least you can get the idea. The mosfet's used as the cascode in the VAS are actually BJT's now because I don't have them yet. But in past experience, they seemed to work better. Will have to experiment to compare for sure. The DC servo circuits work on the principle that Q's 1&2 (N-Ch VAS input) have a Vgs@100uA of -0.5V and Q's 3&4 (P-Ch VAS input) have a Vgs@100uA of 1.8V. If both inputs to the VAS section are grounded (0V), then the result output is -0.6V on both channels, referenced to ground. So in order to get 0VDC for both outputs, both VAS inputs must be on the order of +0.25V. This means the output of the DC servo is always positive and can be referenced to GND instead of -15V. This makes it better for the signal reference too. The floating VAS inputs are driven by two floating outputs from the gain cells.:D They create balanced drive with Av of 4.8 from a single line input. VAS has an Av of 6.2 for an over-all Av of about 30. DC bias and offset is very stable. There are a few more things to tweek but it is working pretty good so far....
 

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CBS240 said:
Hi Kanwar

Now that's an idea that very few on this forum seem to like much. I couldn't agree with you more. It's the way to go about it, IMO. Also you may not need an output coil since there is no GNF loop to corrupt by the components of a nasty reactive load.

THIS circuit has no output coil. There are no zeners in this circuit except for mosfet Vgs protection. I don't like zeners.:yuck: This is the best resolution I can get because of the 100K resolution block in the forum. At least you can get the idea. The mosfet's used as the cascode in the VAS are actually BJT's now because I don't have them yet. But in past experience, they seemed to work better. Will have to experiment to compare for sure. The DC servo circuits work on the principle that Q's 1&2 (N-Ch VAS input) have a Vgs@100uA of -0.5V and Q's 3&4 (P-Ch VAS input) have a Vgs@100uA of 1.8V. If both inputs to the VAS section are grounded (0V), then the result output is -0.6V on both channels, referenced to ground. So in order to get 0VDC for both outputs, both VAS inputs must be on the order of +0.25V. This means the output of the DC servo is always positive and can be referenced to GND instead of -15V. This makes it better for the signal reference too. The floating VAS inputs are driven by two floating outputs from the gain cells.:D They create balanced drive with Av of 4.8 from a single line input. VAS has an Av of 6.2 for an over-all Av of about 30. DC bias and offset is very stable. There are a few more things to tweek but it is working pretty good so far....

Exactly forum members usually like GNFB to get the thing work and generate good THD specs on paper......only few alike us think distinctively.....The schematic looks so wierd just because of very low resolution......and congested drwaing.....I dont want to "jam" my eyesight to view it......already getting a bit of headache :D;)

BTW: You still need to learn how to draw a neat and clean schematic and how to display it on the net........:D :D
 
Your right, the schematic is hard to view, but it was drawn with the intent of helping me build and modify the circuit. If it was all on the computer, it would be too small to see the whole thing. Also I don't have a great electronic drafting program. That is why I just drew it out on a 76cmX127cm piece of cheap partially recycled paper. Not the best medium for posting on the net, but serves the purpose...old school style.:) I may start laying it out in Eagle, just to get some of it entered. Layout is important as with any amp, but with circuit 'modules' and no GNFB, there won't be a NFB loop strung all the way across the PCB. I just realized the all 4 output devices cost $5.20. There is 4 THAT340 transistor arrays at $8 a peice.:xeye: 1 for each input section and 2 for the VAS amplifying transistors. Oh well, they work wonderful and are worth it IMO.:) I haven't been fortunate enough to try out any of thier other products. For example, this could significantly reduce the number of parts in my circuit, as I have basically built a descrete version. http://www.thatcorp.com/datashts/1600data.pdf

More... http://www.thatcorp.com/datashts/1500data.pdf on Mr. Whitlock's common mode bootstrap for this balanced line reciever chip...http://www.thatcorp.com/datashts/1200data.pdf AND some interesting apps. http://www.thatcorp.com/appnotes.html.

Maybe a second thought on using completely descete components might be prudent... but THAT would take all the fun out of it.:D
 
Hi

Not that many here are interested in no global feedback designs, but I have made a significant topology change to the first gain stage/phase splitting circuit. Instead of using two separate amplifier stages, I am now using a balanced bridge. So now I have a balanced bridge driving a balanced bridge.:D I found the symmetry too be much better, faster slew, and fewer components. One would guess correctly that if you input a signal to just the + input, the + output will be larger than the - output, if the load impedance is the same on both sides of the bridge. This obviously will not drive both output's (VAS input's) equally and the circuit wouldn't have equal and opposite outputs. I found that it is the current, not the voltage that must be equal in the bridge. So by putting a 7.5K resistor load on the + output, and a 10K resistor load on the - output, the two output voltages are equal in magnitude. This makes the output impedances of this stage not equal, but they are driving the gates of the next gain stage input J-fets so it doesn't matter. That load is roughly equal to 2K in series with 5pF.
Transistors 1,2,3,4 are a THAT 340 matched array. Both input J-fet pair’s bias @100uA per leg. The 201 has a Vgs@100uA of -0.38V. The 5460 has a Vgs@100uA of 1.8V. This means that the circuit requires a DC servo input of +V on both DC inputs, A & B, in order for both outputs 0 VDC. 'A' is also the signal input as there is an input follower stage preceding this one. I do not find the common mode bias arrangement to affect the signal; rather perhaps acting as a form of EC. Since the circuit is actively biased and DC offset is corrected via DC servo, I have dispensed with the source degeneration on the J-fet's. It doesn't seem to be a problem. Sorry for the old school drawing, it is an excerpt from a larger drawing.
 

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Now that I have installed an input filter, this is the quietest, fastest, most acurate amp I've made so far. You have to put your ear right into the tweeter to hear anything at all, and only in complete silence, when the house fan and the refridgerator compressor is off.:p This I love, it helps that all inportant first watt of power...or maybe it should be the first 1/4W of power.:) This is the new 100KHZ square wave 10V for each side, so 20V and over 2A RMS. 1uS/div. Other than that bit of crossover...:rolleyes: ... that problem is in the output section... some tweeks yet needed there.
 

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