Well, I will of course be testing Ft for the model, so we'll see. Yes, the SOA is the biggest problem with them, especially as they are in a fully insulated case which increases thermal resistance. Very disappointing that they don't offer a version with a metal tab. The 2SC2238/2SA968 have better SOA and a metal tab, but were discontinued by Toshiba. Magnatec/Semelab make their own version (clones rather than fakes), but these are widely counterfeited, I believe.
There is also 2sa1837 2sc4793 with about same spec and in plastic, better SOA than 1930. Toshiba may discontinue the whole lot as they did with 2sa2190 which was to be the replacement for 1930. Well be left with only On semi and Sanken. As for the SOA of 1930 pair i frequently use 2 pairs in paralell.
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Hi Harry,
Its good to hear from you and I appreciate your kind comments about my book. I'm especially glad that you found the SPICE chapters helpful. I'll have to look into those transistors you mentioned. I assume you have seen the device models I posted on my website at CordellAudio.com - Home. BTW, I'm always interested in feedback on the models, since there is always the possibility of errors. Most parts of the models were arrived at by a combination of actual lab measurement on real devices and careful inspection of the datasheets (from multiple manufacturers when possible). Some of the deviations from crappy manufacturer's models were hugely shocking.
Not sure about AES in SF yet, but in any case I'm very interested in any feedback you have.
BTW, I'm writing from Seattle Airport, on a connection to Alaska, for a 2-week Alaska cruise, so my participation on the Forum for the next two weeks will be spotty at best.
Cheers,
Bob
Hi Harry,
That was a good paper and I greatly enjoyed listening to it and meeting you. Thanks for making the updated version available.
Cheers,
Bob
Alaska is big and beautiful. Denali National Park today, Fairbanks tomorrow. Snapped a big Bull Moose today. Gorgeous day.
Cheers,
Bob
As mentioned earlier, I am working on some transistor spice models. I have posted my efforts thus far in this thread, so please head on over there if interested.
One thing I'll say here is that for the single model I've built so far (for the 2SC5707) I had difficulty getting hFE vs Ic and fT vs Ic to match spice vs measured/datasheet. The hFE vs Ic "curve" is extremely flat up until about 3 amps, where it drops very suddenly; this seems to be impossible to match in spice.
For the fT curve, fT "holds up" well until 2 A Ic, when it drops very suddenly, again this seems impossible to model in spice. For fT at low Ic, I couldn't get this to match without upsetting the (currently perfect) match between model and measured for Ceb vs Veb.
If anyone has any advice on how these two things can be fixed/improved, that would be much appreciated.
By the way homemodder, I have now measured the fT vs Ic for the 2SA1930/2SC5171 and got what I'd expect given the datasheets. One thing I did see is that the early voltage of the 2SA1930 is surprisingly low (lower than the Vceo rating) - I measured several devices several times and got the same thing every time. The fT measurements were performed as follows:
S-parameters for the transistors were measured for 300 kHz < f < 3.5 MHz with an HP8573C Network Analyser, 85046A s-parameter test set and custom-built bias-T network. The s-parameters were converted to h-parameters and the fT calculated as h21(@3.5 MHz)*3.5e6. (frequency sweep used to ensure that the high-frequency point was well into the -20 dB/decade roll-off for h21 vs frequency).
One thing I'll say here is that for the single model I've built so far (for the 2SC5707) I had difficulty getting hFE vs Ic and fT vs Ic to match spice vs measured/datasheet. The hFE vs Ic "curve" is extremely flat up until about 3 amps, where it drops very suddenly; this seems to be impossible to match in spice.
For the fT curve, fT "holds up" well until 2 A Ic, when it drops very suddenly, again this seems impossible to model in spice. For fT at low Ic, I couldn't get this to match without upsetting the (currently perfect) match between model and measured for Ceb vs Veb.
If anyone has any advice on how these two things can be fixed/improved, that would be much appreciated.
By the way homemodder, I have now measured the fT vs Ic for the 2SA1930/2SC5171 and got what I'd expect given the datasheets. One thing I did see is that the early voltage of the 2SA1930 is surprisingly low (lower than the Vceo rating) - I measured several devices several times and got the same thing every time. The fT measurements were performed as follows:
S-parameters for the transistors were measured for 300 kHz < f < 3.5 MHz with an HP8573C Network Analyser, 85046A s-parameter test set and custom-built bias-T network. The s-parameters were converted to h-parameters and the fT calculated as h21(@3.5 MHz)*3.5e6. (frequency sweep used to ensure that the high-frequency point was well into the -20 dB/decade roll-off for h21 vs frequency).
Hi Harry,
I experienced the same difficulties when I created the SPICE models for the transistors on my web page, based on the approach that I came up with in my book. I believe a big part of the answer is that the SPICE model does not adequately reflect a good fit to some of these transistor behaviors at high current, and sometimes at low current for ft. A compromize is necessary when trying to match some of the steeper roll-offs of beta at high current for example. There are some tricky tradeoffs among the available parameters. Let me know if you think, based on your experiences in this adventure, if I could do a better job on this sort of thing in my chapter on making transistor models.
For modeling ft at low current, the Cje paraters are quite important, as you know, and yet any direct measurement of Cje under the conditions of forward bias required to operate the transistor can be very difficult.
The one thing I can say with some confidence is that carefully making your own models, making wise compromizes on the match to datasheets or lab-measured performance, will usually yield far better models than those available from many manufacturers. Many are jaw-droppingly bad.
Another very important thing to bear in mind in laboratory measurements on real devices is the effect of junction heating, especially at medium to high collector currents. The temperature dependence of beta can really throw off the measurement of Early effect, for example, often yielding a lower Early voltage than is really the case (if you are looking at Ic vs Vce, as you increase Vce the dissipation goes up). The fairly fast thermal time constant of the transistor die exacerbates this difficulty. On some transistors, when I look at the datasheet curves if Ic vs. Vce, I occasionally wonder if even the factory test/characterization might not have been using a short enough pulse to make the measurement, if they did it with a pulsed DC measurement. Inferring Early voltage from AC measurements can yield better results if done carefully.
Cheers,
Bob
Hi Bob, thanks for the message. I hope you guys enjoyed your holiday!
The modelling of Cje is quite straightforward so it's easy to get SPICE to match perfectly with reality for Ceb vs Veb (i.e. for reverse-biased base-emitter). One assumes that if the reverse characteristic matches perfectly, that the forward model is good, too. At the moment my fT at low currents is too high; I could get this to match better by increasing Cje but then my match of Ceb vs Veb would no longer be perfect
;I'm not sure if that's a good tradeoff?
My measurements weren't pulsed, but were performed as quickly as possible by synchronising two Fluke 8845A multimeters to measure the required voltage and current simultaneously. I could do Ic vs Vbe and Ic vs Vce sweeps in about 20 seconds (the multimeters saving their measurements to internal memory; the measurements then transferred to a PC). The devices had heatsinks attached to try and improve matters as far as possible. In terms of the Ic vs Vbe and Ic vs Vce measurements that I took, I'm happy that what I've got looks realistic.
In terms of modelling hFE vs Ic, this could be improved by removing the IKF parameter, and using a subcircuit model for the bjt that includes a current-controlled current source from base to emitter, whose current depends on collector current and whose function is extracted from the measured hFE vs Ic curve. Two things I'm not sure of is:
Can you have current-controlled current sources in subcircuit models?
How do these arbitrary sources behave in transient and ac analyses?
The modelling of Cje is quite straightforward so it's easy to get SPICE to match perfectly with reality for Ceb vs Veb (i.e. for reverse-biased base-emitter). One assumes that if the reverse characteristic matches perfectly, that the forward model is good, too. At the moment my fT at low currents is too high; I could get this to match better by increasing Cje but then my match of Ceb vs Veb would no longer be perfect
;I'm not sure if that's a good tradeoff?My measurements weren't pulsed, but were performed as quickly as possible by synchronising two Fluke 8845A multimeters to measure the required voltage and current simultaneously. I could do Ic vs Vbe and Ic vs Vce sweeps in about 20 seconds (the multimeters saving their measurements to internal memory; the measurements then transferred to a PC). The devices had heatsinks attached to try and improve matters as far as possible. In terms of the Ic vs Vbe and Ic vs Vce measurements that I took, I'm happy that what I've got looks realistic.
In terms of modelling hFE vs Ic, this could be improved by removing the IKF parameter, and using a subcircuit model for the bjt that includes a current-controlled current source from base to emitter, whose current depends on collector current and whose function is extracted from the measured hFE vs Ic curve. Two things I'm not sure of is:
Can you have current-controlled current sources in subcircuit models?
How do these arbitrary sources behave in transient and ac analyses?
Bob, an update:
I have "completed" my models for the following:
2SC5171
2SA1930
D44H11
D45H11
The models and some other stuff are available in this zip file; the zip includes Excel files which graph measured/datasheet values and those achieved by the Spice models.
I have come to the conclusion that transistors that have a very flat beta vs Ic over a few decades of Ic and then a sudden drop cannot be modelled by a "normal" Spice model. My compromise is to keep beta pretty flat and bear in mind when simulating that beta at high Ic will be overly optimistic in the Spice model. It's possible to get a "better" fit (read: lower rms error over the Ic current range) of beta vs. Ic, by allowing some curvature in the characteristic at low Ic, and making "aggressive" use of the parameter "NK" (not mentioned in your book and not documented in LTspice). However, this leads to greater error in beta at low currents where the real device is flat vs Ic, and also to significant errors in the Ic vs Vbe curve at higher currents. The error in the latter curve can be reduced by using the RBM and IRB parameters, but can't be anywhere close to eliminated because the way RB is varied by RBM/IRB doesn't map well to how beta is being varied by IKF and NK.
By the way, even for transistors with more "gentle" beta vs Ic variation, the NK parameter is still necessary for a good fit. I think you need to investigate this and include details in your second edition.
Moving on to Ft vs Ic:
I did discover that it was possible to increase CJE without too greatly affecting simulated Cbe vs Veb and I have therefore been able to model fT vs Ic at low currents much more accurately. fT at high Ic is still an issue if in the real device it drops-off very suddenly (e.g. the 2SC5707), and also fT at low Vce can be problematic.
As I was trying to improve the models I discovered a series of posts by andy_c, here. I also had a look at his website. He notes on his website that using the parameter "FC", it should be possible to match fT at high Ic better, and that using a more advanced model for transistor saturation should help with fT at low Vce. Unfortunately the "FC" parameter did not behave as I expected and I don't have the time right now to research this further.
With all of that said, I now have models that I'm happy to use; whilst not perfect they're a heck of a lot better than nothing! Maybe one day I'll have time to look into this further.
Does anyone have andy_c's contact details? If so please PM me; I would like to thank him personally for his forum posts, spreadsheet and website as they have all been most helpful.
I have "completed" my models for the following:
2SC5171
2SA1930
D44H11
D45H11
The models and some other stuff are available in this zip file; the zip includes Excel files which graph measured/datasheet values and those achieved by the Spice models.
I have come to the conclusion that transistors that have a very flat beta vs Ic over a few decades of Ic and then a sudden drop cannot be modelled by a "normal" Spice model. My compromise is to keep beta pretty flat and bear in mind when simulating that beta at high Ic will be overly optimistic in the Spice model. It's possible to get a "better" fit (read: lower rms error over the Ic current range) of beta vs. Ic, by allowing some curvature in the characteristic at low Ic, and making "aggressive" use of the parameter "NK" (not mentioned in your book and not documented in LTspice). However, this leads to greater error in beta at low currents where the real device is flat vs Ic, and also to significant errors in the Ic vs Vbe curve at higher currents. The error in the latter curve can be reduced by using the RBM and IRB parameters, but can't be anywhere close to eliminated because the way RB is varied by RBM/IRB doesn't map well to how beta is being varied by IKF and NK.
By the way, even for transistors with more "gentle" beta vs Ic variation, the NK parameter is still necessary for a good fit. I think you need to investigate this and include details in your second edition.
Moving on to Ft vs Ic:
I did discover that it was possible to increase CJE without too greatly affecting simulated Cbe vs Veb and I have therefore been able to model fT vs Ic at low currents much more accurately. fT at high Ic is still an issue if in the real device it drops-off very suddenly (e.g. the 2SC5707), and also fT at low Vce can be problematic.
As I was trying to improve the models I discovered a series of posts by andy_c, here. I also had a look at his website. He notes on his website that using the parameter "FC", it should be possible to match fT at high Ic better, and that using a more advanced model for transistor saturation should help with fT at low Vce. Unfortunately the "FC" parameter did not behave as I expected and I don't have the time right now to research this further.
With all of that said, I now have models that I'm happy to use; whilst not perfect they're a heck of a lot better than nothing! Maybe one day I'll have time to look into this further.
Does anyone have andy_c's contact details? If so please PM me; I would like to thank him personally for his forum posts, spreadsheet and website as they have all been most helpful.
Hi Harry,
This is great work, and I appreciate your suggestions for future versions of my book. Regarding ft droop and beta droop, I FEEL YOUR PAIN!
During the writing of my book I spent many late nights in the lab measuring transistors, gleaning data from datasheets, cursing manufacturers and tweaking SPICE parameters to get a decent fit.
Andy Connors was my inspiration for doing the book chapter on transistor modeling. More than anyone else, he showed how bad many of the commercial models are and how to create better models, even in your garage, if you understood SPICE and had patience.
Andy was especially helpful in leading me in the understanding and creation of EKV models for power MOSFETs.
Andy C is truly missed on this forum. I should note that I am deeply indepted to Andy for another reason: he proof-read my whole book.
Andy's email is (email address removed by moderators).
Cheers,
Bob
Mirrors, but hopefully no smoke
Hi Bob,
Hope all is well with you.
I was reading your book last night, and I came upon Chapter 7, p137, where you say that the VAS operating conditions for a double-input push-pull VAS with current-mirrors are not determined and so the circuit is unusable. (See Fig 7.9.)
I don't follow your thinking here; could you explain a bit more?
Hi Bob,
Hope all is well with you.
I was reading your book last night, and I came upon Chapter 7, p137, where you say that the VAS operating conditions for a double-input push-pull VAS with current-mirrors are not determined and so the circuit is unusable. (See Fig 7.9.)
I don't follow your thinking here; could you explain a bit more?