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Old 18th January 2013, 01:18 PM   #1701
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Originally Posted by DF96 View Post
Increasing the cap size means you droop less. Increasing the transformer voltage means you start higher up. Both mean your minimum voltage is raised. Once the capacitor droop becomes a small proportion of the total voltage drop, as is the case here, then a small increase in transformer voltage does more than a big increase in cap value. This was made clear in the thread, on several occasions.

Am I providing free consultancy for a commercial product development? 8-)
I provide paid for consultancy, thus I remain responsible for the outcome.. I would never trust a DIY doctor if he does not charge me for a professional service.
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Old 18th January 2013, 02:01 PM   #1702
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Old 18th January 2013, 03:22 PM   #1703
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Since I am doing all of this for free, anyway, I would prefer to see the results applied to the development of a commercial product. I am happy for all of the diyers too. But helping someone make a better product, and a profit, is even more gratifying. And if we can also help Nico to look better professionally, and make more money, I can't see any downside to that. Nico did mention, a long time ago, what his intentions were.
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Old 18th January 2013, 03:32 PM   #1704
gootee is offline gootee  United States
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Quote:
Originally Posted by AndrewT View Post
this bounding case is seen as clipping of the signal.
We can see that easily on a scope with both sinewave and with music.
There is a tertiary case: The signal gets progressively more distorted as clipping is approached. I have seen FFT plots showing the increase of high harmonics as clipping is approached. I suspect this tertiary case is showing the effect of non linearity of the amplifier as Vce of some devices becomes similar to Vbe or even worse becomes less than Vbe. As device Vce approaches zero, then we see the bounding case of clipping.
Actually, it would be well-before Vce gets to zero. It would be Vceomin instead of zero, wouldn't it? The amplifier has to have the transistor's minimum voltage plus the voltage across the low-value resistor. If that voltage space is violated, by a ripple voltage minimum dipping into it from above, it will gouge a ripple-shaped chunk out of the output signal's waveform.
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Old 18th January 2013, 03:40 PM   #1705
gootee is offline gootee  United States
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Quote:
Originally Posted by Nico Ras View Post
Tom/DF/Frank,

following is a set of practical measurements from our latest commercial development. After the amplifier design was finalized and frozen the power supply was optimized with the objective that started this thread. The amp is essentially 100 watt into 8 Ohm and I will qualify this so that we are all aware of the criteria used to obtain the results.

The measurement was intended to detect any artifacts in the output signal compared to the input signal added by the amplifier while delivering the rated rms voltage across an 8.2 Ohm resistive load at 20 Hz sine wave input stimulus(mains =50Hz; 240VAC).

The observations were made by comparing the signals between the inverted (NFB) and non-inverted inputs of the amplifier under test using a scope with A-B and dB meter at rated output nulled at 1kHz as reference output.

The amplifier uses four pairs of L-MOSFET as output devices and 0.22 ohm non-inductive drain resistors. There is no current limit applied, no "zobel" across the output nor any series output inductor.

6.3 mm spade terminals were crimped to the caps so that we could connect several in parallel onto an 8 x 8mm copper, positive and negative rail.

A 35 Amp soft recovery fast bridge rectifier type SRDB-3500P-1A was used between the transformer and reservoir without any capacitors across the diodes. We used multiple Hitano ELP range 4700 uF/100V 30 mm diam caps to arrive at an observed optimum value.

We used the same 368VA toroidal transformer wound to supply 36 - 0 - 36 to 46V - 0 - 46 VAC at 2 V intervals (taps) for all measurements.

Our method consisted to set a transformer voltage by connecting to the lowest tap, then starting with 4700uF, and increase the capacitance until the differential voltage on the scope/meter was as low as possible.

If after adding further caps the difference was hard to detect we removed the last cap and returned to the 1 kHz reference signal to make sure this has either improved or remained the same as before.

We then stepped to the next transformer voltage and incremented the capacitance by 4700uF until we reached the point that an observed improvement was uncertain and so on.

The instruments used for this exercise was HP 54645A scope, HP 33120A function generator and HP 33401A multimeter.

The final results was achieved by using four paralleled 4700uF capacitors per rail and 42V setting on the transformer which was higher than one would expect the rail to be for a 100 watt amplifier. In fact the max average power measured with the final settings was 132 watt into 8 ohm (to produce the optimum performance at 100 watt which we find interesting)

Tom/DF/Frank can these observations be verified by any of the theoretical scenario?. There is still a lot of measurements and tests before the amp goes to production, thus I will perform other measurements you may require such as transformer inductance or what-ever is needed to plug into the formulas.

I will not divulge the schematic but it consists of a typical Hitachi topology using double differential amps driving L-MOSFETs, you all know the topology.
I will get back to you in a few hours for more information but your results seem very consistent with everything we have learned here so far.
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Old 18th January 2013, 05:38 PM   #1706
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Originally Posted by jacco vermeulen View Post
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Old 18th January 2013, 09:55 PM   #1707
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Nico,

Did you try it with speakers and music, yet??? :-)

What is the gain, or what was the amplitude of the 20 Hz sine wave input?

What peak and RMS voltages do you see across the MOSFET and resistor, total, with the 20 Hz sine input?

It would be useful if you could measure the transformer parameters, per the procedure at the beginning of the transformer tab in the spreadsheet, for your 42V case. You would probably need a variac (variable transformer).

Do you have a way to measure the ESR of the 4700 uF caps at different frequencies (e.g. 20 Hz), or have some spec?

I can't think of anything else I might need to be able to simulate certain aspects of it, at the moment.

It would be interesting to see the rest of the uF vs Vrms data points that you found, and maybe the A-B measures for them.

Regards,

Tom
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Old 31st January 2013, 01:55 AM   #1708
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Originally Posted by DF96 View Post
If the ripple calculation assumes the worst-case current draw, as it should, then no music current will exceed this. Music at frequencies higher than the (doubled) supply frequency are guaranteed to draw less than the worst case, as for part of the time between charging pulses the music will be drawing current from the other supply rail. Music at frequencies lower than this can only draw the worst case current, and no more. I think we are agreeing?

The only exception to this would occur if capacitor stray inductance (+wiring) caused extra voltage drop for higher frequencies, but in reality this inductance is just as likely to reduce the voltage drop across much of the audio range as it has the opposite sign to the capacitive reactance. Naive bypassing could screw this up, but people using naive bypassing are unlikely to do ripple calcs anyway.

Now if the final PSU cap is well separated (electrically) from the reservoir cap (e.g. by a choke) then the ripple requirements for the reservoir cap and the music current requirements for the final cap get partly decoupled. We can assume the final cap gets fed with a DC current which on average is exactly right to meet music current requirements. The problem now is that the voltage drop in the final cap has to be added on to the average DC droop (i.e. half the maximum droop) in the reservoir cap. We can no longer count on the charging pulse to reset things every 10ms so low frequency requirements are more demanding. So if you have LC smoothing and you want good bass then the final cap may need to be larger than you would need for a single reservoir cap, as it may need to supply current for 25ms (half a cycle at 20Hz) rather than 10ms.
I am getting ready to order 200 electrolytic capacitors, to create two 10x10 "Terry Given" cap-arrays on two 150x203mm two-sided 1mm-thick FR4 PCBs. The 1000uF Nichicon UHE-series caps are 12.5mm diameter max. But the rows of caps will be offset, so the rows can be a little closer than 12.5mm + spacing. But I wan't sure I needed to use 1000 uF caps and wondered if I could possibly use the next-smaller diameter, 10mm.

Unfortunately, the largest 50V value that's 10mm is 470 uF. And their ESR is 2X the ESR of the 1000 uF.

Anyway, I thought that I might as well see what I come up with when calculating the capacitance needed to fully-support perfect bass down to 20 Hz.

My capacitor arrays will function as both the PSU and decoupling caps, because they will fill the space between the rectifiers and the amplifier's output stage. I will most-likely be mounting the output devices (probably a chipamp for initial testing) on a parallel PCB, as close as possible to the rear side of the cap array PCBs (like, 3 mm, but I might try to make it 0 mm, or use some extremely low-inductance connection method; I would hate to get 0.5 nH inductance from the array and then throw any of it away with a stupid connection method). I will place the amp pcb over the junction of the adjacent edges of the two array pcbs (one for each rail), so that the power and ground pins can go directly into the cap array boards' power and ground planes.

If I calculate what would be needed for a full 20 Hz half-cycle without any charging pulses available for 25 ms, then it should be more than enough to be sufficient for most real music, and even for continuous DC at the full peak output voltage, when there ARE charging pulses.

OK. For a 20 Hz sine, if we use:

(17a): C ≥ Δi / ( πf∙(Δv - (ESR∙Δi)))

which is 2x equation (17), to consider the whole half-cycle,

and we use an estimate for the ESR:

ESR = 0.02 / (C x VR), where VR = Voltage Rating of capacitor

and substitute that into (17a), we get:

(18a): C ≥ Δi ((0.04πf / VR) + 1) / (πf∙Δv) [approximate, for electrolytic cap, only]

If we assume that we want Dpct percent voltage droop, then

(19a): Δv = Vsupply∙Dpct/100

and if we leave Vamp Volts for the minimum voltage across the power amplifier, the peak usable output voltage would be:

(20a): Vpk = (Vsupply - Vamp)(1 - (Dpct/100))

and then, with Rload,

(21a): Δi = Vpk/Rload = ((Vsupply - Vamp)(1 - (Dpct/100)))/Rload

We could get an equation for the minimum required capacitance in terms of Vsupply, Dpct, Rload, and the cap's voltage rating VR, by substituting (19a) and (21a) into (18a).

EXAMPLE:

Say we want a 100 Watt RMS sine output power spec, into 8 Ohms. We would need the usable peak voltage to be

(22a): V_usable_pk = sqrt(2∙Rload∙Power_rms)

The minimum power supply peak voltage would then need to be

(23a): Vmin_psu >= (V_usable_pk + Vamp)/(1 - Vripple_percent)

Vmin_psu >= (sqrt(2∙8∙100) + 4)/(0.975) [assuming 2.5% max ripple]

Vmin_psu >= 45.13 V (peak) = 31.91 V RMS minimum transformer secondary rating for 100 Watts into 8 Ohms (or more, if more than 2.5% ripple were allowed) [NOTE that transformer regulation and AC Mains deviations were NOT taken into account.]

So, we will, for now, assume that we can use capacitors rated at VR = 50 VDC, which we will do because lower VR gives a worse case, i.e. larger required C, than higher VR does.

V_usable = 40V peak = 28.28 V RMS

The load current will swing 5 Amps when the voltage across the load swings 40 V. So use Δi = 5 Amps.

Using equation (18a):

C >= (83577 uF) / Δv

Estimated ESR was .02/(.083577 x 50) = 0.0048 Ohm. That appears to be reasonable since an 8200 uF 50V cap was quoted (at mouser.com) as having ESR = 0.04 Ohm and ten of those in parallel would be about 0.004 Ohm.

For 2.5% voltage droop (ripple) with 40 V, Δv = 1 V, giving C >= 83577 uF.

Allowing 10% ripple would give C >= 20900 uF.

Just to check the worst-case upper bound, a square wave, or DC, for 25 ms at 40 V output would require

C >= Δi Δt / Δv (without taking ESR into account)

C >= 5(0.025)/1 = 125000 uF [ = 1.5 * 83577 uF ]

Or, with the same ESR approximation as was used above:

C ≥ (Δi / Δv)∙(Δt + (0.02 / Vrating)) (approximation, for electrolytic capacitors ONLY; NOTE: Used 2x, for DC instead of linear ramp.)

C >= (5/1)(.025+(.02/50)) = 127000 uF

That means that with charging pulses every 10 ms, only 127000(10/25) = 50000 uF should be sufficient, to handle continuous DC output at the rated peak voltage of 40V, without allowing more than 2.5% rail-voltage droop.

So 82000 uF should be enough for a single 20 Hz sine of 100 Watts into 8 Ohms, with <= 2.5% ripple, without being recharged for a full 25 ms half-cycle of 20 Hz.

If being recharged every 10 ms, 33431 uF should be sufficient (i.e. (10ms/25ms)*83577 = 33431), for a single sine, at the maximum rated output power.

So my planned 10x10 array of 1000 uF caps (100000 uF) will be fairly-massive overkill, for 100 Watts into 8 Ohms. But what about 4 Ohms? It turns out that 100000 uF is exactly the minimum required C to supply a continuous 10 Amps of DC current at 40 Volts DC, into 4 Ohms across the output, with less than 2.5% rail voltage droop, if charging pulses occur every 10 ms, and 200 Watts into 4 Ohms only requires 7.07 Amps RMS. So the 10-Amp peaks required for that should be effortless, for these arrays.

The cost of the caps is still worrying me, a little. If I used two arrays per channel, that would be 400 caps. Might as well go for the Qty 500 price break and use 11x11 arrays, in that case. Still, it's a few hundred dollars. Maybe I will think a little longer about either using smaller arrays or smaller-value caps.

Cheers,

Tom

Last edited by gootee; 31st January 2013 at 02:23 AM.
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Old 31st January 2013, 02:03 AM   #1709
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Originally Posted by jacco vermeulen View Post
I don't trust the doctors that do charge either.
Agree Dutchie ....

@Gootee,

Whats the anticipated ripple voltage at full output and what min-z value are you using to determine values, surely not 8ohm ..?
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Old 31st January 2013, 02:44 AM   #1710
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Quote:
Originally Posted by gootee View Post
Unfortunately, the largest 50V value that's 10mm is 470 uF. And their ESR is 2X the ESR of the 1000 uF.
Have a look at Rubycon ZL range - that's showing 330uF/50V in 10mm with a max 100kHz impedance of 28mohm. In my limited experience of extreme paralleling of caps, I found going above 330uF to be problematic in that the self-resonant freq comes down a bit too low for comfort. I doubt when paralleling 100 caps that the high frequency ESR is going to be limited by the caps' ESR, more likely the interconnections.

Quote:
I would hate to get 0.5 nH inductance from the array and then throw any of it away with a stupid connection method).
The inductance seen by the die inside the chipamp package is surely what matters? This to include the total loop area including the die attach wires. Hard to see how that's going to be in the sub-nH territory as the rule of thumb is that for bond wires, the inductance in nH is roughly the length in mm, to a first approximation. The distance between the power pins on your chipamps is going to be higher than 0.5mm.

Quote:
The cost of the caps is still worrying me, a little. If I used two arrays per channel, that would be 400 caps. Might as well go for the Qty 500 price break and use 11x11 arrays, in that case. Still, it's a few hundred dollars. Maybe I will think a little longer about either using smaller arrays or smaller-value caps.
Get someone to source you directly out of Shenzhen I suggest, rather than using local distribution. I just bought 500 390uF/35V Rubycon ZL caps for my chipamps and that order was around $30.
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