Is it just me, or did this thread just go quiet before a lot of interesting questions were answered? For example, why use a complimentary topology - is it to improve the single ended performance? More importantly, why use a su-sys topology for a single ended application - I though the advantages of this were only realised when using balanced output?
It seems there are more questions than answers here. Good! Makes it all the more interesting.
So, the master confirms that SuSy does nothing for single ended output which rather begs the question as to why the UGS circuit (which is SuSy I beleive) is used to convert balanced input to single ended output. Or does it? Perhaps Nelson is dropping another of his crumbs... May be the convertor stage is a simplified version of the UGS, i.e. minus one side of the output which would also remove the SuSy feedback?
Complimentary symmetry to achieve more voltage swing? Perhaps but this could just as easily be achieved by increasing the power supply. Then again JFET's don't in general like a high voltage but one can always cascode to get around that limitation. I still think it must be something to do with achieving better single ended performance. Any thoughts?
So, the master confirms that SuSy does nothing for single ended output which rather begs the question as to why the UGS circuit (which is SuSy I beleive) is used to convert balanced input to single ended output. Or does it? Perhaps Nelson is dropping another of his crumbs... May be the convertor stage is a simplified version of the UGS, i.e. minus one side of the output which would also remove the SuSy feedback?
Complimentary symmetry to achieve more voltage swing? Perhaps but this could just as easily be achieved by increasing the power supply. Then again JFET's don't in general like a high voltage but one can always cascode to get around that limitation. I still think it must be something to do with achieving better single ended performance. Any thoughts?
Unfortunately folded cascode doesn't help in lowering the voltage on the input JFETs. Perhaps this could be another reason for preferring complimentary symmetry though - it avoids the need for output capacitors.
Thanks for the reference to the other thread, I don't beleive I have looked at this previously. Interesting circuit even if if does use bipolars as well as FETs (and could easily be translated into something all-FET).
Thanks for the reference to the other thread, I don't beleive I have looked at this previously. Interesting circuit even if if does use bipolars as well as FETs (and could easily be translated into something all-FET).
Yep, that's what I intended to say 
Folded cascode to get rid of the output capacitor, and active drain loads to shield the input fets against high voltages. And again, the voltage swing is limited by the cascode biasing voltage (the drain voltage can't go higher...)
But obvioulsy it doesn't answer our questions ...
And 2 cents more
Folded cascode to get rid of the output capacitor, and active drain loads to shield the input fets against high voltages. And again, the voltage swing is limited by the cascode biasing voltage (the drain voltage can't go higher...)But obvioulsy it doesn't answer our questions
...And 2 cents more
I recall the X pre is an extension of the Su patent.
+- inputs and =-tputs, small fets cacoding the dual Jfet inputs..
Thee are advantges in amplifying balanced inputs without converting to SE and then back to balanced outputs...as this can be done with a single stage.
I suppose even a stripped down X Aleph without the Aleph cs would work....just scale the parts and go from there.
The J fets have the advantage of self biasing when used in pairs and have lower noise.
Macka
+- inputs and =-tputs, small fets cacoding the dual Jfet inputs..
Thee are advantges in amplifying balanced inputs without converting to SE and then back to balanced outputs...as this can be done with a single stage.
I suppose even a stripped down X Aleph without the Aleph cs would work....just scale the parts and go from there.
The J fets have the advantage of self biasing when used in pairs and have lower noise.
Macka
Darry said:
For a power amp example, look at the attachment at the end of this post:
http://www.diyaudio.com/forums/showthread.php?postid=334963#post334963
Or just cut the feedback trace (R14+R18) in my schematic here in this very thread: http://www.diyaudio.com/forums/showthread.php?postid=614603#post614603
Tino
acaudio said:
If someone is interested, the pcb layout of my testboard can be found on http://www.acaudio.de/UGS_3_cascode.pdf
Adam
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