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Old 14th October 2009, 09:23 PM   #21
smyslow is offline smyslow  Europe
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Join Date: Feb 2009
Location: Villach
Hi Ian,

enclosed a picture of my UGS board, the schematic and FFT plots.

The first FFT is from the soundcard in loopback mode only. The second FFT is with soundcard and UGS board. For the measurements I used a Terratec Phase26 USB. As I mentioned yesterday, it has only single ended inputs and outputs. Therefore the second FFT plot shows only the spectrum of the positive output voltage. A more professional soundcard with balanced inputs and outputs like the E-MU 0404 would be better for my requirements. The software I've used is RMAA from Audio Rightmark. It is available for free. SpectraPLUS is more powerful and more adequate for such measurements, but it is not for free, after trial period of 30 days you have to buy the software.

Sorry for the bad quality of the board picture.

Uwe
Attached Images
File Type: jpg UGS_diyAudio_Board.jpg (75.5 KB, 483 views)
File Type: jpg Terratec-Phase26_diyAudio_FFT_1kHz.jpg (45.9 KB, 465 views)
File Type: jpg UGS_diyAudio_FFT_1kHz.jpg (46.3 KB, 455 views)
Attached Files
File Type: pdf UGS_diyAudio_Simulation-Schematic.pdf (22.0 KB, 124 views)
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Old 14th October 2009, 10:04 PM   #22
smyslow is offline smyslow  Europe
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Quote:
Originally Posted by Ian Macmillan View Post
Not sure about compensating for the loss of gain by decreasing R6 though. This will increase the current in both input and second stages but I doubt it will have a huge impact on gain. The gain is determined largely by the ratio of R12 to R7 (and the same for the other three quadrants).

Ian.

Of course you're right. Maybe it was too late yesterday evening

For keeping the same OLG for the second stage in case R6 is decreased the source resistors of the mosfets have to be increased as well.

It seems to be hard to find the optimum operating conditions for your requirements (high CL gain, high CL bandwith, less neg feedback, high output voltage swing). My requirements are more relaxed. Basically I need only a single to balanced converter with some gain in the range of 2 for driving my balanced F5.

Nevertheless, I think spice simulations are best suited for such optimizations. Do you have appropriate models for the mosfets you use? So far I haven't found spice models for IRF610/9610 on the net.

Regards, Uwe
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Old 15th October 2009, 09:42 AM   #23
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Uwe,

Thanks for publishing your circuit and distortion measurements. I'll investigate both the software and sound cards you mention (I'm no expert in either).

Regarding your comments on my requirements, I'm afraid you are exactly right in it being difficult to meet all the requirements. Increasing the output device source resistors for example compromises both the output swing and decreases the overal gain. Also the diff pair current cannot be reasonably increased beyond a certain point (less than Idss) to accommodate the signal swing. That is why I suspect I will need to find some better output devices. I will check that it is these that are dominant first though although I suspect the diff pair cascoding will give a wide bandwidth in the first stage.

I do have models for IRF610, 9610 and similar (I am actually using IRF510 and SFP9510 in my circuit). I can publish these if you like but I don't have them on this computer so it will have to be later.

Ian.
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Old 15th October 2009, 07:08 PM   #24
smyslow is offline smyslow  Europe
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Ian,

as promised, some scope plots. The input voltage (top trace) is 10Vpp, the middle and bottom traces are the output voltages. The left plot is with 10kHz, the right one with 50kHz.

I would be glad if you would post the spice models for IRF610/9610 and/or IRF510/9510 you use. Thanks a lot.

Have you checked if Toshiba offers mosfets with lower Cgd? I'm thinking about to replace the IRFs with 2SK2013/2SJ313 in my UGS.

Regards, Uwe
Attached Images
File Type: jpg UGS_#2_Rect_20Vpp_10kHz.jpg (28.9 KB, 405 views)
File Type: jpg UGS_#2_Rect_20Vpp_50kHz.jpg (29.4 KB, 396 views)
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Old 16th October 2009, 04:54 PM   #25
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Hi Uwe,

I would say the performance you are seeing with a 50KHz square wave is pretty impressive. Why do you want to change the MOSFETs? The Toshiba devices you mention are laterals and hence have lower transconductance (0.7S) than the IRFs (2S). They also have a lower Vgs so you will need to change the resistor values round a bit. Given that they don't have that much lower Cgd (17 rather than 20pf) I am not sure it would be worth the change.

I have a few suggestions to make regarding your circuit which I will try and write up shortly and post. Maybe you will like them but even if not, hopefully food for thought or experimentation.

I'll post the spice models this weekend when I have access to my home computer.

Ian.
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Old 16th October 2009, 11:13 PM   #26
smyslow is offline smyslow  Europe
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Hi Ian,

I agree with you that the mentioned Toshibas don't have the better spec then the IRFs. I'm just curious because I use 2SK1530/2SJ201 in my F5 and I'm very happy with the resulting bias stability and sound, both is a bit better then with IRFP240/9240. The latter is of course very subjective. So maybe one day I give them a try. But they are expensive and it's hard to find them.

Please feel free to post any suggestions about the circuit, I appreciate any new ideas and thougths. That's the reason why we are here, isn't it?

Regards, Uwe


BTW, Fairchild seems to have promising mosfets too, like the FQP5N50C and FQP3P20.
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Old 17th October 2009, 10:11 AM   #27
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Hi Uwe,

Spice models as promised:

.model IRF610 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=100n Uo=600 Phi=.6 Rs=.5804 Kp=20.77u W=.45 L=2u Vto=3.886
+ Rd=.5781 Rds=888.9K Cbd=220.5p Pb=.8 Mj=.5 Fc=.5 Cgso=517.7p
+ Cgdo=61.68p Rg=.2597 Is=1.647p N=1 Tt=295n)
*$
.model IRF620 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=100n Uo=600 Phi=.6 Rs=.114 Kp=20.39u W=.23 L=2u Vto=3.083
+ Rd=.3209 Rds=888.9K Cbd=650.2p Pb=.8 Mj=.5 Fc=.5 Cgso=3.996n
+ Cgdo=168.7p Rg=7.473 Is=59.21p N=1 Tt=610n)
*$
.model IRF9610 PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=100n Uo=300 Phi=.6 Rs=.721 Kp=10.37u W=.64 L=2u Vto=-3.814
+ Rd=1.524 Rds=888.9K Cbd=222.3p Pb=.8 Mj=.5 Fc=.5 Cgso=1.517n
+ Cgdo=30.29p Rg=2.4 Is=886.1E-18 N=4 Tt=1100n)
*$
.model IRF9620 PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=100n Uo=300 Phi=.6 Rs=.339 Kp=10.15u W=1.4 L=2u Vto=-3.735
+ Rd=.6365 Rds=888.9K Cbd=426.4p Pb=.8 Mj=.5 Fc=.5 Cgso=1.359n
+ Cgdo=32.22p Rg=1.106 Is=48.34E-18 N=3 Tt=670n)
*$
.model IRF510 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=100n Uo=600 Phi=.6 Rs=.4508 Kp=20.68u W=.64 L=2u Vto=3.697
+ Rd=21.08m Rds=444.4K Cbd=366.5p Pb=.8 Mj=.5 Fc=.5 Cgso=600.5p
+ Cgdo=62.71p Rg=2.977 Is=202.9f N=1 Tt=135n)
*$
.model IRF9510 PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=100n Uo=300 Phi=.6 Rs=.3715 Kp=10.54u W=.2 L=2u Vto=-3.923
+ Rd=.4523 Rds=444.4K Cbd=331.8p Pb=.8 Mj=.5 Fc=.5 Cgso=2.547n
+ Cgdo=311p Rg=4.087 Is=2.896E-18 N=3 Tt=2250n)
*$

Ian.
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Old 17th October 2009, 11:02 AM   #28
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Hi Uwe,

I like the spec of the Fairchild devices too but I think they are fairly hard to get of now as they are no longer made.

Some suggestions for your circuit which I think means you really don't need better devices. Note the results are simulations so reality may be a little different.

As drawn:

o/l gain: 50dB, -3dB 55KHz
c/l gain: 3.2dB, -3dB 255kHz
Feedback: 46dB

Change:

R17/19 to 700R (to discard some feedback)
R11/12 to 24K (to restore gain)
C1/2 to 2.2p

Gives:

-3dB 1.4MHz
Feedback: 17dB

And a very clean 50kHz square wave!

Just an idea. Have fun experimenting.

Ian.
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Old 17th October 2009, 10:05 PM   #29
smyslow is offline smyslow  Europe
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Hi Ian,

thanks a lot for the spice models! And many thanks for your suggestions too. I will implement the changes within the next days and give you a feedback.

Uwe
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Old 18th October 2009, 04:33 PM   #30
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I've done some more measurements on my circuit in open loop to try and find out from where the lack of speed originates. The rise time at the output of the diff pair (including cascodes) without the output devices connected is 11uS at a level of 1v p/p which is the level needed to drive the output to the required maximum level. This seems slow to me (I was expecting something nearer 1uS). Connecting the output devices through the 220R resistors decreases this to 35uS which is less of a reduction than expected.

So the conclusion would appear to be that I have an issue with the diff pair + cascodes. I'm running the diff pair at 4.6mA per device and the voltage across each JFET is around 5.5v.

Anyone able to offer any suggestions?

Ian.
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