I'm building an XA100 varient and have started testing the UGS front end before I connect it up to the output boards. Unfortunately it seems I have a problem: the UGS oscillates at around 700KHz even with the inputs shorted.
So far the only cure I have found is to either load each output with around 1nF or place 4.7pf caps across feedback resistors R23 and R24. Unsurprisingly, both result in poor HF response.
The real question is why does the circuit spontaneously oscillate in the first place? Is there something poor in my PCB layout (double sided, fairly conventional), do I need an earth plane? Perhaps the problem would be resolved by increasing the gate stopper resistors to say 470R?
I've not read of others experiencing this problem so I must have done something pretty stupid.
Help, anyone?
Ian.
So far the only cure I have found is to either load each output with around 1nF or place 4.7pf caps across feedback resistors R23 and R24. Unsurprisingly, both result in poor HF response.
The real question is why does the circuit spontaneously oscillate in the first place? Is there something poor in my PCB layout (double sided, fairly conventional), do I need an earth plane? Perhaps the problem would be resolved by increasing the gate stopper resistors to say 470R?
I've not read of others experiencing this problem so I must have done something pretty stupid.
Help, anyone?
Ian.
A bit thank you Nelson for your advice 
The cascode bias arrangement is not something I would have considered as there seem to be plenty of other similar designs (e.g. Chef's UGS-P) that use a similar arrangement apparently without issue.
If I recall correctly, you did mention in a previous post that you had learned some interesting things about biasing the cascodes but I don't remember seeing any subsequent detail. Is this something you might share soon?
In the meantime I will explore ways to reduce the AC impedance and report back.
Ian.
The cascode bias arrangement is not something I would have considered as there seem to be plenty of other similar designs (e.g. Chef's UGS-P) that use a similar arrangement apparently without issue.
If I recall correctly, you did mention in a previous post that you had learned some interesting things about biasing the cascodes but I don't remember seeing any subsequent detail. Is this something you might share soon?
In the meantime I will explore ways to reduce the AC impedance and report back.
Ian.
Well I finally found time to experiment a little here and am reporting back as promised. I did the simplist thing I could think of seeing as my layout for the moment precludes more than simple experimentation (a lesson to learn here). I connected each cascode base to ground with a 0.1uF capacitor, 4 in total. The result? Much better
Open loop -3dB frequency went from 14 KHz to56 KHz and the closed loop from 69 KHz to 178 KHz. Better still, a 10 KHz square wave now looks very reasonable, just a hint of high frequency roll off and no sign of any instability. Thanks very much for your help Nelson.
I am still intrigued why others haven't seen this problem but I guess that will just have to remain a mystery unless someone would care to share their experience. I'm also interested in other solutions, such as a proper DC supply for the cascodes with low impedance at all frequencies. Maybe I will get around to trying these out sometime.
Ian.
Open loop -3dB frequency went from 14 KHz to56 KHz and the closed loop from 69 KHz to 178 KHz. Better still, a 10 KHz square wave now looks very reasonable, just a hint of high frequency roll off and no sign of any instability. Thanks very much for your help Nelson.
I am still intrigued why others haven't seen this problem but I guess that will just have to remain a mystery unless someone would care to share their experience. I'm also interested in other solutions, such as a proper DC supply for the cascodes with low impedance at all frequencies. Maybe I will get around to trying these out sometime.
Ian.
Hi Ian,
Your idea with the caps is very neat. It had not my first thought when I originally read this thread.
Your resistor chain is about 53K and draws about 1.4ma. I would have halved the values of the resistors for starters or reduced the values in the chain as low as possible without the dissipated power becoming greater than one third of the resistor power rating. That would avoid adding any ground connections.
If you're willing to add connections to ground then putting zener diodes to ground from the bases is another idea - about 7.5V to 9.1V.
Cheers,
Graeme
Your idea with the caps is very neat. It had not my first thought when I originally read this thread.
Your resistor chain is about 53K and draws about 1.4ma. I would have halved the values of the resistors for starters or reduced the values in the chain as low as possible without the dissipated power becoming greater than one third of the resistor power rating. That would avoid adding any ground connections.
If you're willing to add connections to ground then putting zener diodes to ground from the bases is another idea - about 7.5V to 9.1V.
Cheers,
Graeme
Thanks for the benefit of your replies Graeme and Zen Mod.
I did think about reducing the values of the bias resistors as you suggest Graeme, but to tell the truth I am not sure how low an impedance I need to solve the problem. The issue is primarily AC impedance, hence my decision to use caps to ground. I also considered the zener approach (with cap bypass) but this would dump more current to earth than I would prefer. I still might try this out though.
Not sure about bypassing the 8K8 resistor as you suggest Zen Mod - how would this reduce the impedance seen by the cascode gates? I did try something similar which didn't seem to work very well although I was using flying leads which I am sure wouldn't have helped.
Another option I considered was bypassing the resistors between gates and power supplies, i.e. 4 in total. This would reduce the AC impedance but I suspect would also add ripple and noise so I didn't take it any further.
Ian.
I did think about reducing the values of the bias resistors as you suggest Graeme, but to tell the truth I am not sure how low an impedance I need to solve the problem. The issue is primarily AC impedance, hence my decision to use caps to ground. I also considered the zener approach (with cap bypass) but this would dump more current to earth than I would prefer. I still might try this out though.
Not sure about bypassing the 8K8 resistor as you suggest Zen Mod - how would this reduce the impedance seen by the cascode gates? I did try something similar which didn't seem to work very well although I was using flying leads which I am sure wouldn't have helped.
Another option I considered was bypassing the resistors between gates and power supplies, i.e. 4 in total. This would reduce the AC impedance but I suspect would also add ripple and noise so I didn't take it any further.
Ian.
another one - you can see that Papa ( from his own reasons ) is always biasing cascodes against ground .......... not sources of jfets/mosfets .
I have impression that putting at least 1mA through bias voltage divider for smaller cascode parts (TO92) is always enough , but for bigger ones double or triple can't do any harm .
anyway , whenever I try to anticipate Papa's reasons , seems that I'm right only in one case - to confuse spoiled children .......
seriously - it's easy to solder plain 4u7 elco across that 8k8 ;
try that ...... if not good , you can always say that ZM is dumb , not you
edit :
even without trying cap across that resistor , you can say that ZM is dumb , not you .........
I have impression that putting at least 1mA through bias voltage divider for smaller cascode parts (TO92) is always enough , but for bigger ones double or triple can't do any harm .
anyway , whenever I try to anticipate Papa's reasons , seems that I'm right only in one case - to confuse spoiled children .......
seriously - it's easy to solder plain 4u7 elco across that 8k8 ;
try that ...... if not good , you can always say that ZM is dumb , not you
edit :
even without trying cap across that resistor , you can say that ZM is dumb , not you .........
Nelson Pass said:
Interesting and I have to admit not something I had even considered. I've avoided referencing the cascode bias to sources more because of the need to deal with the bias current than anything else.
I recall the load line effect being used in your power JFET application but hadn't appreciated it might apply to this low power situation too (OK, not quite the same as we are not talking about modulation here - or are we?). I'll take a look at the graphs for the dual JFETS to see if I can understand the details.
Thanks as always for the tip.
Ian.
Poor rise time
I thought I had this cracked with the help of the Master's tip about the cascodes but it seems I have another issue.
The rise time for the UGS I've built is poorer than expected, about 1v/us open loop, 10KHz -3db point. Is this as would be expected? I thought (hoped?) for something closer to 10v/us or better. Currently I need more feedback than I wish to use to correct.
My suspicion are the IRF510/9510 or at least the samples I have. Can anyone confirm? I've tried looking for some faster devices to try but without much luck. Perhaps the 2sk213/j76 laterals but these have much lower transconductance.
I've been playing with various ideas without much success so would appreciate some help.
Ian.
I thought I had this cracked with the help of the Master's tip about the cascodes but it seems I have another issue.
The rise time for the UGS I've built is poorer than expected, about 1v/us open loop, 10KHz -3db point. Is this as would be expected? I thought (hoped?) for something closer to 10v/us or better. Currently I need more feedback than I wish to use to correct.
My suspicion are the IRF510/9510 or at least the samples I have. Can anyone confirm? I've tried looking for some faster devices to try but without much luck. Perhaps the 2sk213/j76 laterals but these have much lower transconductance.
I've been playing with various ideas without much success so would appreciate some help.
Ian.
Hi Ian,
yesterday i finished my second version of a UGS. For my first build I took the one posted here: http://www.diyaudio.com/forums/showthread.php?p=1002713 (the version with bjt current mirrors for the output stage). My actual version is identical to your version but with different transistors and resistor values. I use IRF610/9610 for output stage, BC550/560 for cascodes and 2SK170/2SJ74 for input stage. I had problems with oscillations too. A small capacitance of 22pF across the feedback resistor fixed this problem. But compared to your design I use feedback resistors of only 22k and not of 510k as shown in your schematic (R23, R24) from the first post of this thread. With only 22k feedback resistance I have no issues with bandwith. Why do you need such a high gain? This is something around 30dB closed loop gain.
I have no possibilities to measure the frequency response, only to simulate it. I will try to measure the slew rate and distortion spectrum (with a soundcard). I just checked the DC stability of the output voltages (very stable!) and connected the UGS to my balanced F5. And the sound is very promising
Regards, Uwe
yesterday i finished my second version of a UGS. For my first build I took the one posted here: http://www.diyaudio.com/forums/showthread.php?p=1002713 (the version with bjt current mirrors for the output stage). My actual version is identical to your version but with different transistors and resistor values. I use IRF610/9610 for output stage, BC550/560 for cascodes and 2SK170/2SJ74 for input stage. I had problems with oscillations too. A small capacitance of 22pF across the feedback resistor fixed this problem. But compared to your design I use feedback resistors of only 22k and not of 510k as shown in your schematic (R23, R24) from the first post of this thread. With only 22k feedback resistance I have no issues with bandwith. Why do you need such a high gain? This is something around 30dB closed loop gain.
I have no possibilities to measure the frequency response, only to simulate it. I will try to measure the slew rate and distortion spectrum (with a soundcard). I just checked the DC stability of the output voltages (very stable!) and connected the UGS to my balanced F5. And the sound is very promising
Regards, Uwe
Thanks for both your replies.
Uwe: glad your UGS sounds promising and I look forward to seeing your measurements.
I was really looking for what sort of bandwidth and rise time could be expected from this circuit used open loop so that I can see how much feedback will be needed to achieve the desired 100KHz, 50v/us closed loop result. I believe Nelson manages this in his XA series amplifiers with less feedback than my result of 1v/us would require. Come to that, a quick simulation shows an open loop result of 9v/us but I don’t totally trust these things. I strongly suspect that samples of IRF510/9510 to have more capacitance than they should and am trying to confirm before I go off and purchase a whole load more (need quite a few to obtain some matched samples).
Based on the datasheets, IRF610/9610 have more capacitance than 510/9510 which is why I chose the latter. I’d happily use something else if I could find devices with lower capacitance.
Why do I need so much gain? I’m using my UGS to drive an XA100 type output stage, i.e. 10 pairs of MOSFETS per side and around 26dB of gain (as measured) is about right for this application. To lower the feedback resistors would also mean lowering the value of the input resistors and hence make the amplifier harder to drive.
SuSy works best with relatively low feedback, hence I don’t wish to simply apply more feedback. I’d also rather avoid the additional complexity (and likely sound degradation) of solutions such as cascoding the second stage.
I don’t think increasing R6 will have any effect on bandwidth other than negatively by lowering both the diff pair and output current. I could add small source resistors which may well be a positive influence although I seem to remember Nelson saying that he preferred the sound without, preferring instead to “throw away” some feedback by using resistors from virtual earth point to ground.
My goal is to try and achieve the 100KHz, 50v/us result with just 6dB of overall loop feedback which implies that my open loop needs to be much better than it is. I suppose another option would be to nest feedback loops and apply some feedback just around the UGS to improve its performance. Even so I think I need a better basic performance. Or perhaps I don’t?
Anyone care to offer any other opinions?
Ian.
Uwe: glad your UGS sounds promising and I look forward to seeing your measurements.
I was really looking for what sort of bandwidth and rise time could be expected from this circuit used open loop so that I can see how much feedback will be needed to achieve the desired 100KHz, 50v/us closed loop result. I believe Nelson manages this in his XA series amplifiers with less feedback than my result of 1v/us would require. Come to that, a quick simulation shows an open loop result of 9v/us but I don’t totally trust these things. I strongly suspect that samples of IRF510/9510 to have more capacitance than they should and am trying to confirm before I go off and purchase a whole load more (need quite a few to obtain some matched samples).
Based on the datasheets, IRF610/9610 have more capacitance than 510/9510 which is why I chose the latter. I’d happily use something else if I could find devices with lower capacitance.
Why do I need so much gain? I’m using my UGS to drive an XA100 type output stage, i.e. 10 pairs of MOSFETS per side and around 26dB of gain (as measured) is about right for this application. To lower the feedback resistors would also mean lowering the value of the input resistors and hence make the amplifier harder to drive.
SuSy works best with relatively low feedback, hence I don’t wish to simply apply more feedback. I’d also rather avoid the additional complexity (and likely sound degradation) of solutions such as cascoding the second stage.
I don’t think increasing R6 will have any effect on bandwidth other than negatively by lowering both the diff pair and output current. I could add small source resistors which may well be a positive influence although I seem to remember Nelson saying that he preferred the sound without, preferring instead to “throw away” some feedback by using resistors from virtual earth point to ground.
My goal is to try and achieve the 100KHz, 50v/us result with just 6dB of overall loop feedback which implies that my open loop needs to be much better than it is. I suppose another option would be to nest feedback loops and apply some feedback just around the UGS to improve its performance. Even so I think I need a better basic performance. Or perhaps I don’t?
Anyone care to offer any other opinions?
Ian.
Regarding the simetrix version of post 1:
Did you take the rise time of the source into account?
In simetrix the default seems to be 100nS per volt at 10Khz. Unless you set this specifically
this could ruin any conclusions.
R27 and R28 (500 ohm) are a heavy load on your input. I suppose these help the output DC offset.
But don't they have a rather nasty side effect on the slew rate?
If these questions are stupid, do not hesitate to say so.
regards
Did you take the rise time of the source into account?
In simetrix the default seems to be 100nS per volt at 10Khz. Unless you set this specifically
this could ruin any conclusions.
R27 and R28 (500 ohm) are a heavy load on your input. I suppose these help the output DC offset.
But don't they have a rather nasty side effect on the slew rate?
If these questions are stupid, do not hesitate to say so.
regards
Hi rtirion, thanks for staying with me on this thread.
Your questions are not stupid and I will try and address them.
I didn’t take into account the rise time of the Simetrix source so thanks for alerting me to this. That said, 100ns per volt is perfectly fast enough for my application and in any case the rise time of the circuit in the simulator looks fine. It is real life which differs, unfortunately in the wrong direction.
I checked the rise time of my signal generator and it is 25ns per volt so no problem there.
R27 and R28 are indeed low values but I’m not sure what you mean by heavy on the input. They are connected at a virtual earth point so the source will see the 15k series resistor pretty much irrespective of the values of R27 and R28. Perhaps you are referring to the gate of the JFET as the input here?
The purpose of R27 and R28 is to “throw away” some feedback rather than control the DC offset which is fairly well behaved anyway. These resistors attenuate the input and feedback by roughly the same amount and can be used to control the amount of overall feedback applied. The 500 ohm value was my attempt to apply just 6dB of overall feedback. I’ve tried adjusting this to vary the amount of feedback and of course the rise time of the output does improve with higher values due to the additional feedback. However, I’d prefer not to be applying 30+ dB feedback around the whole circuit as I mentioned before.
As far as I see it I have only two options: try and improve the basic open loop rise time which I believe to be a function of the device capacitances or perhaps use a feedback loop round the UGS and another round the entire circuit, i.e. including the output stage. Given my UGS open loop rise time of 1v / us this still means I need a lot of feedback round the UGS stage though.
I’m coming to the conclusion that Nelson’s XA100 circuit is really quite a delicate balancing act in order to get it right. Basically open loop performance must be balanced with appropriate levels of feedback against the various circuit capacitances. I’ve a feeling the gate stopper resistors on the output followers may well be part of this balance. I’m using 150 ohm but I suspect I may need to reduce to increase the capacitive load on the UGS output if I am going to use much feedback here (to help control the overshoot on a square wave). Of course I could apply frequency compensation elsewhere but I’d rather leave that as a last resort.
Perhaps I am going nowhere with this line of reasoning but I think I will persist a little longer and also hope for another crumb or two from the Master.
Ian.
Your questions are not stupid and I will try and address them.
I didn’t take into account the rise time of the Simetrix source so thanks for alerting me to this. That said, 100ns per volt is perfectly fast enough for my application and in any case the rise time of the circuit in the simulator looks fine. It is real life which differs, unfortunately in the wrong direction.
I checked the rise time of my signal generator and it is 25ns per volt so no problem there.
R27 and R28 are indeed low values but I’m not sure what you mean by heavy on the input. They are connected at a virtual earth point so the source will see the 15k series resistor pretty much irrespective of the values of R27 and R28. Perhaps you are referring to the gate of the JFET as the input here?
The purpose of R27 and R28 is to “throw away” some feedback rather than control the DC offset which is fairly well behaved anyway. These resistors attenuate the input and feedback by roughly the same amount and can be used to control the amount of overall feedback applied. The 500 ohm value was my attempt to apply just 6dB of overall feedback. I’ve tried adjusting this to vary the amount of feedback and of course the rise time of the output does improve with higher values due to the additional feedback. However, I’d prefer not to be applying 30+ dB feedback around the whole circuit as I mentioned before.
As far as I see it I have only two options: try and improve the basic open loop rise time which I believe to be a function of the device capacitances or perhaps use a feedback loop round the UGS and another round the entire circuit, i.e. including the output stage. Given my UGS open loop rise time of 1v / us this still means I need a lot of feedback round the UGS stage though.
I’m coming to the conclusion that Nelson’s XA100 circuit is really quite a delicate balancing act in order to get it right. Basically open loop performance must be balanced with appropriate levels of feedback against the various circuit capacitances. I’ve a feeling the gate stopper resistors on the output followers may well be part of this balance. I’m using 150 ohm but I suspect I may need to reduce to increase the capacitive load on the UGS output if I am going to use much feedback here (to help control the overshoot on a square wave). Of course I could apply frequency compensation elsewhere but I’d rather leave that as a last resort.
Perhaps I am going nowhere with this line of reasoning but I think I will persist a little longer and also hope for another crumb or two from the Master.
Ian.
Hello Ian,
Thanks for the answers.
One more question: What is/was the frequency and amplitude of the input signal when you measured the slewrate of the amp?
clear. Aprox -30dB att. Example: From a 1Vp diff input signal roughly 33mVp
reaches the gates of J-Fets.
However, I am still trying to understand how this network attenuates the feedback.
Thanks for the answers.
One more question: What is/was the frequency and amplitude of the input signal when you measured the slewrate of the amp?
The source sees 15k-500-500-15k diff. This resistive attenuation network is
clear. Aprox -30dB att. Example: From a 1Vp diff input signal roughly 33mVp
reaches the gates of J-Fets.
However, I am still trying to understand how this network attenuates the feedback.
Hi Ian,
for increasing the OLG bandwith you have to move the dominant pole to higher frequencies. If the dominant pole is defined by the second stage, then you can decrease the gain of this stage by decreasing R4 & R5, i.e the miller capacitance decreases as well. Of course the gain loss of the second stage has to be compensated with a higher gain of the first stage (lower R6, higher IDSS) if you want the same OLG as before. Just some ideas, maybe it helps.
This evening I've done first distortion measurements with my UGS version. My soundcard has only singe-ended inputs, so I couldn't check distortions of the balanced output voltage. Both single ended voltages have only H2 at something around -60dB. This is quite a high value but i hope the balanced susy topology will remove most of the H2 on the balanced output voltage. If I find some time tomorrow evening I will post the schematic and some FFT plots.
Regards, Uwe
for increasing the OLG bandwith you have to move the dominant pole to higher frequencies. If the dominant pole is defined by the second stage, then you can decrease the gain of this stage by decreasing R4 & R5, i.e the miller capacitance decreases as well. Of course the gain loss of the second stage has to be compensated with a higher gain of the first stage (lower R6, higher IDSS) if you want the same OLG as before. Just some ideas, maybe it helps.
This evening I've done first distortion measurements with my UGS version. My soundcard has only singe-ended inputs, so I couldn't check distortions of the balanced output voltage. Both single ended voltages have only H2 at something around -60dB. This is quite a high value but i hope the balanced susy topology will remove most of the H2 on the balanced output voltage. If I find some time tomorrow evening I will post the schematic and some FFT plots.
Regards, Uwe
Rtirion:
I’ve actually tried several variations for frequency and amplitude with similar results but my preferred values are:
- 1KHz square wave for open loop testing
- 10KHz square wave for closed loop
I use whatever input amplitude is required to achieve full output (but less than full supply rail to rail), i.e. about 80v pk/pk. This requires 4v pk/pk input for the closed loop case, rather less for open loop but I don’t recall the exact figure offhand.
I’m measuring slew rate by calculating the time it takes for the leading or trailing edge of the wave to travel 90% of the total amplitude. I think this is the normal method of establishing rise time but please correct me if I am mistaken.
Others have written in some detail on the effect on feedback of the resistors to ground. In summary, the resistor returns some of the feedback to ground and it turns out in practice that this attenuation is approx the same as the amount by which the input is attenuated. Chef de Gar on this forum covered this mathematically, noisefree performed a number of practical measurements which confirmed. My practical results seem to concur.
Uwe:
Agreed I need to move the dominant pole to a higher frequency. I also admit that at this point I am assuming it is the second stage miller capacitance as you say – I suppose I should verify this. I hadn’t thought about decreasing R4 and R5, mainly because this will work the second stage harder which may not be desirable (but I don’t know this for sure). I’ll give this a go and report back on what happens.
Not sure about compensating for the loss of gain by decreasing R6 though. This will increase the current in both input and second stages but I doubt it will have a huge impact on gain. The gain is determined largely by the ratio of R12 to R7 (and the same for the other three quadrants).
Look forward to seeing your results. Come to that I would be interested in what software and sound card you use to do this. I would like to be able to measure distortion and hence will need to invest in something like this or find a used distortion analyser. Probably the latter would be best but I’m not sure where to look nor how much something half decent might cost.
Ian.
I’ve actually tried several variations for frequency and amplitude with similar results but my preferred values are:
- 1KHz square wave for open loop testing
- 10KHz square wave for closed loop
I use whatever input amplitude is required to achieve full output (but less than full supply rail to rail), i.e. about 80v pk/pk. This requires 4v pk/pk input for the closed loop case, rather less for open loop but I don’t recall the exact figure offhand.
I’m measuring slew rate by calculating the time it takes for the leading or trailing edge of the wave to travel 90% of the total amplitude. I think this is the normal method of establishing rise time but please correct me if I am mistaken.
Others have written in some detail on the effect on feedback of the resistors to ground. In summary, the resistor returns some of the feedback to ground and it turns out in practice that this attenuation is approx the same as the amount by which the input is attenuated. Chef de Gar on this forum covered this mathematically, noisefree performed a number of practical measurements which confirmed. My practical results seem to concur.
Uwe:
Agreed I need to move the dominant pole to a higher frequency. I also admit that at this point I am assuming it is the second stage miller capacitance as you say – I suppose I should verify this. I hadn’t thought about decreasing R4 and R5, mainly because this will work the second stage harder which may not be desirable (but I don’t know this for sure). I’ll give this a go and report back on what happens.
Not sure about compensating for the loss of gain by decreasing R6 though. This will increase the current in both input and second stages but I doubt it will have a huge impact on gain. The gain is determined largely by the ratio of R12 to R7 (and the same for the other three quadrants).
Look forward to seeing your results. Come to that I would be interested in what software and sound card you use to do this. I would like to be able to measure distortion and hence will need to invest in something like this or find a used distortion analyser. Probably the latter would be best but I’m not sure where to look nor how much something half decent might cost.
Ian.
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