UGS Problem

[Ian Macmillan]

Were the additional source resistors placed between R6 and the sources of the JFETs? And what's with the open loop gain? I assume it decreases a bit with the additional source resistors.

Indeed they were, 4 in total. The open loop gain dropped to 29.6dB using 4 x 20R resistos.

I assume this is the influence of the gain bandwith product. With R25=15k and R27=3.7k the attenuation is 0.2 (-14dB). With R27=200k the attenuation is 0.93 (-0.63dB). The ratio of both values gives 0.215. Multiplicated with the old corner frequency of 200kHz gives a new corner frequency of only 43kHz. (Or in a few words: gain x corner frequency = constant.) Of course this is only true if the open loop gain increases with increasing of R27. Is this the case? If yes, then maybe the dominant pole is defined by the collector resistance R8 and base-collector capacitance of the BJTs and not by the input resistance (R25||R27) and input capacitance of the JFETs. But I'm not sure if this is really true. I'll try to do some simulations with different BJT models.

Perhaps I don't understand GBP as I thought it only applied to the case where negative feedback is used to decrease the gain. In this instance, the combination of R25 and R27 only acts to attenuate the signal, i.e the open loop gain remains unchanged if the signal is viewed at the gate of input JFET. The gain is obviously less if measured from the input node, i.e. the input end of R25.

I'm still inclined to think that the dominant pole as you call it, is most likely defined by the input resistance and input capacitance of the JFETs which is R25||R27 as you say assuming the internal impedance of the signal source is zero. This would seem to be confirmed by the -3dB frequency increasing with lower values of R25, irrespective of R27. Not sure what this means with respect to your calculated ratio though which seems to match reality rather well.

A few days ago I've tried your suggestions regarding my UGS. Low open loop gain rules! It gives definitely the better sound. Drawback is the poorer dc offset stability (maybe more 1/f noise). Unfortunately I haven't found time to do some measurements so far.

Pleased to learn that it sounds better although I suspect it is low closed loop gain that is the key here

Ian.

 

[Itsmee]

Have a look at the AMB beta24 amplifier, it may have some answers.


HeadWize: DIY Workshop > β24: A discrete, cascoded, fully-differential power amplifier

 

[Ian Macmillan]

Have a look at the AMB beta24 amplifier, it may have some answers.

Thanks for the advice but I've looked at this design before and I am not sure which aspect you think might be relevant here. I know I could cascode my quad CS stage but I'm trying to avoid that for now as I don't believe it should be necessary. Not sure I'm ready to start trying cascode output stages as there is a considerable body of opinion that feels that these often lack dynamics. I don't have any first hand experience though. Have you heard the beta24?

Ian.

 

[smyslow]

Perhaps I don't understand GBP as I thought it only applied to the case where negative feedback is used to decrease the gain. In this instance, the combination of R25 and R27 only acts to attenuate the signal, i.e the open loop gain remains unchanged if the signal is viewed at the gate of input JFET. The gain is obviously less if measured from the input node, i.e. the input end of R25.

I'm still inclined to think that the dominant pole as you call it, is most likely defined by the input resistance and input capacitance of the JFETs which is R25||R27 as you say assuming the internal impedance of the signal source is zero. This would seem to be confirmed by the -3dB frequency increasing with lower values of R25, irrespective of R27. Not sure what this means with respect to your calculated ratio though which seems to match reality rather well.

It seems that I was wrong with my assumptions. Sorry for the confusion.

Pleased to learn that it sounds better although I suspect it is low closed loop gain that is the key here

The closed loop gain of my ugs remains the same as before. If a lower resistor between virtual ground and gnd gives less feedback than the open loop gain decreases by the same amount the feedback decreases. Or I am wrong again?



A few posts before you wrote that you will try some new devices for the output stage. If possible, please post your findings, I'm sure they would be interesting for many of us.

Regards, Uwe

 

[Ian Macmillan]

It seems that I was wrong with my assumptions. Sorry for the confusion.

What I said was just my interpretation of what is happening based on my measurements. I don’t claim to be an expert and I could just as easily be wrong as you.

The closed loop gain of my ugs remains the same as before. If a lower resistor between virtual ground and gnd gives less feedback than the open loop gain decreases by the same amount the feedback decreases. Or I am wrong again?

Hmm… I suspect both of us may be wrong. Of course, the closed loop gain is the same. Not so sure about the open loop gain though. It is true that the resistor between virtual ground and signal ground both attenuates the feedback and the signal. Whether this should be construed as reducing the open gain depends on how you look at it. The gain as seen from the input has certainly been reduced, but the overall gain looking into the gate remains the same. Anyway, perhaps this is just playing semantics – I think we were both trying to say that low overall feedback rules.

A few posts before you wrote that you will try some new devices for the output stage. If possible, please post your findings, I'm sure they would be interesting for many of us.

I hadn’t forgotten but thanks for keeping me honest.

My new devices eventually arrived (FQP5N20 and FQP5P20 for those interested in the details) and I set about matching them. No problem with the N-N and P-P matches but I suspect I must have been exceptionally unlucky with my samples as the N-P matches were about as far out as it is possible to be within the specs. The N devices have a Vgs of around 1.9v for my target Id of 25mA whilst the P devices require around 4.5v. This is the biggest difference I have encountered to date. Unfortunately these devices are now obsolete and obtaining additional samples from a different lot is not really an option.

Clearly I cannot just drop these into the existing circuit as they will be way outside the range of the offset adjustment pot. Adding an additional resistor between pot (VR1) and power rail would address the DC bias but messes up the AC conditions (more gain on +ve signal swing than –ve). I’m not sure what is the best approach here but options I am considering are: bypass the additional resistor with a suitable cap, use a number of forward biased diodes or a shunt regulator to ground. The cap is easiest but would need to be a big value and doesn’t address the sensitivity of the DC offset to the diff pair current. Probably one of the other options is better but I would appreciate any view on this.

I’m also unsure whether it even makes sense to use such mismatched devices in practice. If the variance in Vgs is the only difference then probably it doesn’t matter. If this also implies other differences, e.g. in gm or whatever, then it is not so great. Probably I will look for some other options (maybe 2SK216/2SJ79 or similar) but in the meantime I wanted to at least try the latest devices to see if their reduced Crss had the expected effect.

Using a resistor and bypass cap for this purpose, I measured the following. Open loop gain 56dB, -3dB point 15.5kHz with a slew rate of about 1v/uS measured single ended. This shows the anticipated improvement over the previous (IRF510/IRFP9510) measurements of -3dB point 10.5kHz and slew rate of 0.65v/uS. Good!

So far I have only made one closed loop measurement with the SE gain set at 26dB and around 16dB of feedback (around 14dB of feedback being thrown away by the 3.7k resistor from virtual earth to ground). This yielded a -3dB point of 133kHz and slew rate of 6.5v/uS measured single ended.

The bottom line is that the Fairchild devices improve the performance by roughly a factor of 2. Good news but likely to give a final differential slew rate of 24v/uS with the intended configuration and gain, i.e. still only roughly half the target value. I will confirm this with measurement shortly.

Ian.