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Old 13th June 2008, 04:19 AM   #91
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Default JFET Biasing

Hi Ken,

The Fet circuit shown in Don Tillman's article is very similar to the circuit that I had written about in my previous postings. If you have not read my previous postings, this may be a good time to do so.

In any case, the amplifier is a self-biased, common-source design using the J201 JFET. The key term here is "self-bias", which simply means that the amp will bias up to a steady-state (or, quiescent) condition that is totally dependent on the devices "transfer characteristics" (again, this is explained in my previous postings).

In any class-A, linear amplifer (e.g. the Tillman design) you should bias the device so that the DC value at the output (in this case, the Drain) is equal to between 1/2 and 2/3rds that of the power supply (in this case, a nine-volt battery). This will ensure a relatively "equal" swing of an AC signal above and below the DC value at the Drain before "clipping" occurs.

When Tillman said that the DC value should be between 5 and 7 volts, he was referring to the voltage you would measure relative to the negative terminal (or "zero" volt reference) of the nine-Volt battery. This would mean that you have between 4 and 2 volts across the 6.8KOhm Drain resistor. According to Ohms law, this would also mean a bias current between 0.588mA and 0.294mA through the J201 (in the interest of conserving battery-life, I biased my amp to 0.1mA).

It is interesting to note that the J201 JFET I evaluated for the amplifier in my previous postings would not have worked well with Mr. Tillman's design. However, Tillman does say this when he mentioned that not just any J201 would work with the values he chose for his circuit. He suggests that you try a handful of them before you can find one that works well.

On the other hand, by evaluating the JFET and determining it's transfer characteristics (not a difficult thing to do as explained in my pervious postings) you can customize Mr Tillman's common-source, self-bias design for optimal performance (or, in other words, excellent symmetry about the Drain DC bias value).

Please let me know if this helps; if you have any questions, please do not hesitate to ask.

Thanks, JP Hugsley
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Old 13th June 2008, 06:08 AM   #92
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First, thank you for your response!
Yes, I have read your previous postings on the subject though I didn't understand everything. I'm getting back into electronics after retiring from a career of programming so I need to brush up on terminology and theory. Also, much of this is new to me as most of my experience has been with opamps where my main considerations were gain and cutoff frequencies.

I think that perhaps I should consider using your schematic rather than Mr. Tillman's for a few reasons:
-It would conserve battery life a bit more.
-Am I correct in my impression that yours is not quite as picky about the particular JFET used?
-I like your gain figures better (6.8). And..
-I've exhausted all 10 of my transistors searching for one with the proper characteristics. There's no electronics store near me so I must wait for ordered parts.

I will try evaluating the FETs I have and study more carefully how to customize the circuit for proper performance
.
One question: If I use your circuit would the 10mfd decoupling cap across the battery still be a good idea?

You've been a great help and I really appreciate your time and effort.
Thanks again,
Ken
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Old 13th June 2008, 03:41 PM   #93
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Mr. Hugsley,
After rereading your posts I realize now that the schematic you posted is the first stage of a guitar preamp. I thought it was the whole preamp due to its similarity to Donald Tillman's. Would it work without a second stage? What would be the advantages of a second stage?
Thanks,
Ken
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Old 14th June 2008, 04:47 AM   #94
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Default JFET Bias

Hi Ken,

There is really no difference between the design that I posted and that of Mr. Tillman. They are both common-source JFET amplifiers; the difference is in the device itself. Even though they are both J201 devices, the variation in IDSS and VGSoff among J201 type JFETs is rather large. If you refer to a data sheet, you may be surprised to see that the IDSS for the J201 can be between 0.2mA and 1.0mA. In addition, the VGSoff can be between -0.3V and -1.5V.

From what I can tell, the device used in the Tillman design is on the high-side of the specification scale. In other words, the device he used most likely has an IDSS of 1.0mA and a VGSoff of -1.5V. The reason that I believe this is because he mentioned that the bias current in his circuit is about 0.5A. This means that the VGS is about 1.1V (0.5mA*2.2KOhm = 1.1 Volt) and the voltage drop across the Drain resistor (R3) is 3.4 Volts (0.5mA*6.8KOhm = 3.4Volts). This, of course, means that the Voltage at the drain of the J201 is 5.6 Volt (9Volt - 3.4 Volt = 5.6Volt).

(If any of this is not clear, please let me know and I'll explain it with a sheet of equations and diagrams).

The J201 device that I used in my circuit had a measured IDSS of 510uA and a VGSoff of -0.77Volts. If I had used my J201 in Mr. Tillman's design, it would not have worked very well (if at all). The bias conditions for my design were chosen to fit the particular J201 I had in my shop; this is what must be done when using the self-bias technique to ensure proper operation. From what you have told me, I believe the J201s that you have in your possession are probably more middle-of-the-road devices rather than the high-end-of-the-spectrum device Mr. Tillman used. In other words, there is nothing wrong with your JFETs, you just have to change the circuit values to best suit them.

Try changing the values of Mr. Tillman's design with one of your JFETs by making R3 = 20KOhm, R2 = 2.0KOhm and R4 = 10KOhm. R3 and R2 will give you a gain of nearly 7.0 (like my design) but R4 will load-it-down to a gain of about 2.0 (this is how you "tame the thing" as you called it).

In any case, don't throw away your JFETs, just evaluate them for IDSS and VGSoff as I described in my previous postings and then select component values to ensure optimal operation (biasing).

Again, if any of this in not clear, please let me know and I will make an effort to produce a paper that is more professional and concise.

Also, a 10uFd decoupling cap is a good idea to have on the circuit board as near to the active device(s) as possible. This will provide a zero-Ohm Voltage source for your circuit and help prevent issues with stray impedances.

Also again, the second-stage device on the design I was talking about in my postings will be an emitter-follower using a BJT. The advantage to an emitter follower stage is to isolate your active device and tone circuitry from the un-predictable loading effects of your guitar cable and guitar amp input impedance. This will become clearer in a future posting but, first, you should evaluate your JFETs and then optimize your common-source circuit design.

I hope this helps.

JP Hugsley.
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Old 16th June 2008, 03:03 AM   #95
xavmdq is offline xavmdq  Argentina
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Hi JP Hugsley:

Sorry for delay to answer (In this week I have 2 exams and I don't have much time).

The guitar is a Steinberger Synapse EMGSYN-GP-1. I don't have information about piezo. Check this page to see a picture.

In these days I'll make transfer curves using 5 or 6 2N3819 I have (In my city there are no J201 FET). I check a 2N3819 and obtain an Idss=1.3mA and Vp=-2.5V.

In these post and following I'll show my actual circuit. My idea is to replace equalizer with jfets (if possible) to reduce current consumption and the possibility to adjust circuit elements to achieve the best performance and low consumption.
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Old 16th June 2008, 03:05 AM   #96
xavmdq is offline xavmdq  Argentina
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Equalizer:
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Old 16th June 2008, 03:10 AM   #97
xavmdq is offline xavmdq  Argentina
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Mixer:
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Old 16th June 2008, 12:55 PM   #98
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Hi, my name is Julián and live in Buenos Aires, how many J201 do you need ?
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Old 16th June 2008, 01:59 PM   #99
xavmdq is offline xavmdq  Argentina
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Hi Julian,

I need between 10 and 20 (I have to select the best for this circuit). My mail is xaviermdq arroba yahoo.com.ar.

Javier


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Originally posted by Andronico
Hi, my name is Julián and live in Buenos Aires, how many J201 do you need ?
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Old 16th June 2008, 03:17 PM   #100
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@ J. P. Hugsley

Hi,

I have evaluated my JFETs, writing their Idss and Vgsoff values on masking tape for future reference. I'm still not clear on how exactly to calculate the surrounding components for optimal results. I'd like to bias the amps at 0.1ma as you have to conserve batteries. I've read and reread your posts and though I have a much greater understanding of how the amp works, I guess I'm missing something. Can you point me to equations I can apply to calculate values for target currents and gain factors?

I'm happy to say that I built an amp following your recommended values as closely as I could: R3 = 21.5 k, R2 = 2.15k and R4 = 10k. This gave a voltage at the Drain of slightly over 6 volts. I know that's a little high but the amp does work so I tried it in my guitar. It's still slightly strong, overdriving the digital effects device I use unless the volume on the guitar is turned down to half or less, but usable. I noticed that when the guitar volume is turn down to 1 or 2 (out of 10) the high frequencies are being damped. Should I put the preamp between the pickup and the volume control? Also, should there be a DC blocking capacitor at the output?
Anyway it's working for now and I await your post of the second stage so I can build the complete preamp.
I really appreciate all your help and patience with one in unfamiliar territory. Instead of blindly following a schematic and a parts list with no explanation I am coming to understand how these work and learning to design my own.
Thank you very much,
Ken
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