Jitter blocking

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
Jump to Latest
Nixie

Nixie

Banned
Joined 2006
I read that ASRCs like the AD1890 convert input jitter to slight amplitude errors. Does your chip avoid that?

For example, from this post,
Windowed "real time" ASRC upsampling where the source clock
is monitored with relation to the destination clock and the calculations are done based on instananeous clock relationships. The reason the clock relationships are used is to keep synchronization. This means the jitter on the source clock is encoded into the calculated data. You then also get jitter on the destination clock. This is the method used in those ASRC chips for external DACs (and some use them for one box upsampling players although this seems insane since now you have 2 clocks worth of jitter to worry about)
Click to expand...
 
B

Bruno Putzeys

Member
Joined 2004
hypex.nl
dusfor99 said:
Which window? Blackman-Harris..Hann..?
Click to expand...
I've cobbled together a variation on a gaussian window that works well (better than a straight gaussian). We can talk about it over email.

Re missed samples, would it help to use a fifo of a few samples and to have the PLL bandwidth scale according to the absolute time error? Some people simply use a stepped bandwidth with low-med-hi settings.
 
D

dusfor99

Member
Joined 2006
Nixie said:

How is that possible? I've read many times that ASRCs only attenuate input jitter, not null it.
Click to expand...


Hi Nixie,

That depends on how you do the SRC. In the one I did does not do what any onther ASRC does to convert the stream (that I have come across). Since the input data stream is "perfect" I can SRC it into a much better clock domian (the xtal). When I say the input stream is perfect, what I mean is that every sample is exactly the AMPLITUDE it is supposed to be. The jitter simply puts that sample off in time by a slight amount. I guess the right thing for me to do is to not claim what it can do but to do some tests on it that you would like to see and post the results. If you (or anyone) want to see some kind of test, please let me know and ill be glad to do them.


CLD
 
D

dusfor99

Member
Joined 2006
Nixie said:
I read that ASRCs like the AD1890 convert input jitter to slight amplitude errors. Does your chip avoid that?

For example, from this post,
Click to expand...


Hi Nixie,

Good thread link. The line at the end of the post you quoted says "delta sigma" might be a solution to a lot of these problems realy hits home with this ASRC. How about instead of just saying it gets rid of it all, (because it is possible to degrade the SRC performance with INSANE amounts of jitter, which some ASRC wont even be able to get a lock, CS8421) i wil do the tests you require. I am often guilty of over simplifying my posts and I like the fact that i get questioned on it.


CLD
 
D

dusfor99

Member
Joined 2006
Bruno Putzeys said:

I've cobbled together a variation on a gaussian window that works well (better than a straight gaussian). We can talk about it over email.

Re missed samples, would it help to use a fifo of a few samples and to have the PLL bandwidth scale according to the absolute time error? Some people simply use a stepped bandwidth with low-med-hi settings.
Click to expand...


I see where your going with this. Hmmm, so trade-off the "PLL" bandwidth with some extra delay in the ASRC. I will put some thought into this and see if I can do something along the lines. WOW, lots of great suggestions here, I wish I had come to this site long ago.


CLD
 
D

dusfor99

Member
Joined 2006
rfbrw said:



Talking of marketing, what is the target market for this device?
Click to expand...


To be honest, I dont really know. Im just the chip designer. Another engineer and I (actually my boss) thought it was a cool new way to do SRC, so we made a chip for it. THen we compared it to the CS8421 in the lab to make sure it was atleast as good as it. Then once the performance was good, we sent out some engineering samples to a company in Edmonton (Canada) and they were currently using the CS8421. They liked the simplicity of our design so much they wanted to design it into their refference designs within a week of getting the part, but then we ran into the problem that they needed large quantities about 3 months before we would have them.


CLD
 
D

dusfor99

Member
Joined 2006
Hi All,


Well here in an update on the ASRC chips. The new rev is due back early this week. This has a couple bugs fixed. I should be getting back about 35 samples or so. RIght now I have a small ASRC test board that has an SPDIF Input and Output, and It also has the serial data Input and Output connected to a header. Im sorry its taking a bit of time, but its due to delays in packaging. Anyways, I will be able to sample a few of the ASRC's to a couple people, its just going to take a little bit longer. As part of giving the samples away all I ask is for a little bit of feedback, just to let me know how the part is working. How the "sonics" are and yadda yadda. In about 3 weeks time I plan to have a single tiny board that has the ASRC + DAC so thats something thats up an comin.



CLD
 
roender

roender

Member
Joined 2006
dusfor99 said:

As part of giving the samples away all I ask is for a little bit of feedback, just to let me know how the part is working. How the "sonics" are and yadda yadda. In about 3 weeks time I plan to have a single tiny board that has the ASRC + DAC so thats something thats up an comin.

CLD
Click to expand...

dusfor99, I will be your beta tester if you can send me two samples with specs.
As for ASRC dimmension, in what type of package will be encapsulated?

Thank you
 
FastEddy

FastEddy

Member
Joined 2006
4ourbees.com
dusfor99: " ... I guess the right thing for me to do is to not claim what it can do but to do some tests on it that you would like to see and post the results. If you (or anyone) want to see some kind of test, please let me know and ill be glad to do them. ..."

But of course!! Please let us all know how your tests work out.

Also: I would be very interested in the Edmond (Canada) company's effort using your new chip. My (state side) company is always interested in new, unique and worthwhile products in esoteric and not so esoteric markets. Please contact me or email to: support@firewirestuff.com

Thx

Ed Karns
3DotAudio.com and more

(" ... In about 3 weeks time I plan to have a single tiny board that has the ASRC + DAC so thats something thats up an comin. ..."
I would like to obtain one of your boards as well, if possible, but I don't know when I would have the time to evaluate it, what with the several class-d & MOSFET amps we have on the skillet now ... I may have to wait for the "whole goods" to do justice ... keep the faith, the digital audio world is just now trampling the beginnings of a path to your door.)
 
FastEddy

FastEddy

Member
Joined 2006
4ourbees.com
related link: http://focus.ti.com/docs/prod/folders/print/src4392.html ... just got this in the email today ...

" ... Two-Channel Asynchronous Sample Rate Converter (SRC)
Dynamic Range with -60dB Input (A-Weighted): 144dB typical ... :eek:
Total Harmonic Distortion and Noise (THD+N) with Full-Scale Input: -140dB typical ... >>= popcorn noise?
Supports Audio Input and Output Data Word Lengths Up to 24 Bits ... :eek:
Supports Input and Output Sampling Frequencies Up to 216kHz ... :apathic:
Automatic Detection of the Input-to-Output Sampling Ratio ...
Wide Input-to-Output Conversion Range:
16:1 to 1:16 Continuous ... :apathic:
Excellent Jitter Attenuation Characteristics ... :rolleyes:
Digital De-Emphasis Filtering for 32kHz, 44.1kHz, and 48kHz Input Sampling Rates ... :bawling:
Digital Output Attenuation and Mute Functions
Output Word Length Reduction ... :confused:
Status Registers and Interrupt Generation for Sampling Ratio and Ready Flags
Digital Audio Interface Transmitter (DIT)
Supports Sampling Rates Up to 216kHz ... :apathic:
Includes Differential Line Driver and CMOS Buffered Outputs ...
Block-Sized Data Buffers for Both Channel Status and User Data
Status Registers and Interrupt Generation for Flag and Error Conditions
User-Selectable Serial Host Interface: SPI or Philips I2Cª ... :apathic:
Provides Access to On-Chip Registers and Data Buffers ..."

This is "Rev B" ? Rev C might be your competition "real soon now"?

dusfor99: You might have this one beat ... (Big companies have big overhead, big admin ... and big, fat "time to market" curves ... 1K samples = US$10 ea. ... :>)

:smash:
 
gbyleveldt

gbyleveldt

Member
Joined 2006
I actually received some of the SRC4392's on sample, I just haven't had the time to play with it! I have it good authority that these are pretty good, especially in the jitter department. I'm going to reserve comment till I have time to play with it, though. The only problem is that, for simple stereo operation, is like hitting a fly with a tank. I think these are better suited for AV receivers, but if the specs are anything to go by, then I don't care!

Cheers

Gert
 
D

dusfor99

Member
Joined 2006
Hi Nixie,


Yes, there is some. I have got the ASRC chips back, there is a minor issue, but nothing that prevents them from being evaluated. If you could send me a personal email, discuss more then.

Anyone else who has experience withe ASRC's and would like to "beta" test one, please send me an email. The reason I ask for people that have experience is because there is no formal datasheet at the moment, but someone that is quite familiar will be able to get it running no problem.


Thanks


CLD
 
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
Top Bottom