A nice feature, if possible, is to do pure upsampling by 2 or 4 without any LPF, i.e. simple zero stuffing to increase the sampling rate going downstream to some other interpolation filter and dac. I suppose this could be added to your ROM register for implementing different filters, except this will be considered the 'no filter' case.
The reason for upsampling is that some slow roll-off filters have sub-optimal out of band attenuation and compromised base band response that can be solved by upsampling.
The reason for upsampling is that some slow roll-off filters have sub-optimal out of band attenuation and compromised base band response that can be solved by upsampling.
I just read the datasheet of the AD chip and there's something I don't understand about ASRCs. Rather than compute the filter value at the precise sample time location, they say they have 2^20 values and then decimate. Why can't you just use a DSP to compute it on the fly? Then you don't have to deal with the error of chosing a nearest one in a fixed set (and on top of this, since they can't store 2^20, they interpolate between them, so even more error). In other words, why not use arithmetic instead of memory (lookup table for the filter)?
Ok, I will try to put together some kind of datasheet and get you a part.
The package is 28pin TSOP. Yes it does include the SPDIF reciever. On the current rev of the chip, the SPDIF input is a standard input pin, so to work for all sample rates, an exturnal comparator is needed to garantee that the spdif signal is large enough to trigger the schmidt trigger on the input pad. This will be put internal on the Mass Production version of the chip.
Im a bit confused here. If I was to just upsample a signal without an anti-aliasing filter an then put it through some slow roff off filter, you would have a bunch of images that you didn't get rid of in the output. Is there an application that this would be useful for?
I agree. That is how this ASRC was implemented. Its not done like any other one on the market. (Or so I beleive)
Wow, a 48pin package to SRC 2 channels. Well that 20 more pins for 1. Another thing is that on the ASRC i designed, there is not need for the control interface. It is completely configurable by pin-strapping. So you can choose I2S/LJ/RJ in 16/20/24/32 bit formats or SPDIF for the input. And the same goes forthe output. There are 4 mode_in pins to set all these modes for input, and 4 mode_out pins to set the output data format. So it is a very easy chip to implement. Again ill try get a preliminary datasheet for you guys to look over.
CLD
I was considering using the SRC4392 myself on my new DAC. I just hadn't had time to finish the design, but have a couple of samples on hand. I figured it would have a fair amount of trial and error to work, as there is hardly any info except for the datasheet (meaning reference design to get you started quickly)
I'm quite curious about your product as well!
I'm quite curious about your product as well!
dusfor99 said:
By slow roll-off filter, I mean it's an interpolation filter with the stopband attenuation relaxed to supposedly give better transient response. If you refer to the pcm1794 datasheet, the 'slow roll-off' interpolation filter has a -3db cutoff at roughly 0.5Fs. So for a sampling rate of 44.1KHz, we are already getting -3db rolloff at 20KHz. If we upsample before sending data to the pcm1794, the interpolation filter will process the 2x data (zero-stuffed) at the 2x rate, and push all the images up by the interpolation factor, which (correct me if I'm wrong) if zero-stuffing is done beforehand, the actual interpolation factor will be twice what was designed for the pcm1794.
John Swenson, who is a forum member here, actually upsampled the data before it hits the interpolation filter and dac, and has claimed that he achieved the best sonics. I am interested in doing something like that, but without a cpld/fpga, implementing upsampling involves quite a few chips if we want to shift the data 32 or 64 times.
rlim said:
Ok, I see where your going with this. What your trying to do is have more samples to put into the DAC so it may have a better transient responce.
Im not familiar with Johns design and what he really did, but if you take a data source at say 44.1kHz and put a zero between every sample so you now have data at 88.2kHz and feed that to the DAC so the DAC thinks it getting a 88.2kHz, then the PCM1796 slow rolloff filter will not be able to supress the images that lie in the 24.1kHz to 0.5(-6dB) *88.2kHz = 44.1kHz. So basically, you will have all the images from 24.1kHz to 44.1kHz that the DAC is now letting through since it thinks its getting a 88.2kHz. Now here is where its gets interesting. Since what has really happened is we have just pushed the filter cuttoff to a higher frequency the transient responce will be better. However the images will all still get though, but can you or me actually hear them? (Thats a whole new thread on its own) I guess its hard to say what quantifies what one person calls "best sonics" to what another might.
Just one think to note. If you add a some 0's but dont make sure you remove the images, then just dont take a look on a scope of the output of the DAC with a 20kHz tone going into it, then all will be good. If you do, the 20kHz tone wil look very wierd and its because it is 20kHz + 24.1kHz. and you never removed the 24.1kHz.
CLD
ezkcdude said:
If you use the AD1896, then the images will be attenuated due to the built-in filter. Some don't like ASRC claiming that they can hear things that are unpleasant. I myself wonder if it's due to this anti-aliasing filter, or if it's due to the jittery input coming in, which is eventually converted into voltage noise. It would be interesting to block jitter before it gets to the ASRC, i.e. via secondary pll, and then use the ASRC to double the sampling rate and see what the outcome is through listening. Sorry I digress.....
Dustin, with regards to the problem of bandwidth, a suggestion is to provide hooks to adjust the bandwidth, together with an error signal pin such that if there's too much jitter, the pin will indicate to the user to increase the bandwidth. This will also allow users to optimise their system for lowest incoming jitter and utilize your ASRC in the lowest bandwidth setting for maximum performance.
rlim said:
rlim,
Yes this is a good idea and I will put some provision for that in the next rev. I had planned to do this before but I thought the compromise I came up with was "good enough" but if people want to tweak every once of performance, its simple to make it like that. Plus not to mention the hours of fun that can be had tweaking it.
CLD
ezkcdude said:
I cant say what the jitter is on others parts, but I can tell you that the jitter coming off the part I made is only dependent off the xtal or (whatever kind of clock source you use). So if you use a good xtal, the jitter is going to be very very low.
By the way I dont think I mentioned this, but I have also designed a DAC. the first test samples only came in with a DNR of -118dB so we are making changes. I have a protype in the lab running at -128dB, so that is our target. Just thought I would mention that too to see if anyone had some "cool features" that a DAC might want to have.
CLD
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