Hi,
I'm planning to build a dac and I like to know how I can reduce the jitter. Now I know two different styles:
a) Using asynchronous sample rate converter (like AD1896)
b) Using spidf receiver and spidf transmitter:
http://www.akm.com/AppsNotes/Reclocker.htm
Which one would give better results in theory? What about the other jitter reducion techniques?
I'm planning to build a dac and I like to know how I can reduce the jitter. Now I know two different styles:
a) Using asynchronous sample rate converter (like AD1896)
b) Using spidf receiver and spidf transmitter:
http://www.akm.com/AppsNotes/Reclocker.htm
Which one would give better results in theory? What about the other jitter reducion techniques?
dump USB and use 1394, connect directly to I2S = no detectible jitter.
See any 1394 DAC from these guys: http://m-audio.com and http://rolandus.com
( http://industrialcomponent.com/firewirestuff/fws46603.html )
See any 1394 DAC from these guys: http://m-audio.com and http://rolandus.com
( http://industrialcomponent.com/firewirestuff/fws46603.html )
In my opinion adding random jitter is equivalent to blocking jitter, since it can cover regular jitter. The Nyquist frequency is especially sensitive to jitter, since it is phase-fixed (at least for acoustic music, electronic sound can be phase-fixed at any frequency). A method of adding random jitter more selectively to the Nyquist frequency would be the following:
*filter and upsample 32 times
*devide into blocks of 16 subsequent values
*use a random generator to select one of each block
*do 15th order interpolation
*filter and upsample 32 times
*devide into blocks of 16 subsequent values
*use a random generator to select one of each block
*do 15th order interpolation
Guido Tent: " ... I2S has no data induced jitter as the clock is separate, the resulting jitter still depends on the clock quality. Best is to have the clock at the DAC, [with] the source acting as a slave [, slaved to the DAC clock]. In that case SPDIF also works well as interface best ..." (Pardon my editing above, a bad habit picked up techie geek white paper rewrites)
Mr. Tent has some other interesting thing to say on his web site about jitter, DACs & CD/DVD player quality: http://www.tentlabs.com/Products/cdupgrade/index.html ... http://www.tentlabs.com/Products/diycd/index.html ...
(One would hope that he will follow through soon with a "universal" DVD-A / SACD / DVD-V player or upgrade or possibly even a kit !! I would buy one in a New York minute ... do you take PayPal?)
Mr. Tent has some other interesting thing to say on his web site about jitter, DACs & CD/DVD player quality: http://www.tentlabs.com/Products/cdupgrade/index.html ... http://www.tentlabs.com/Products/diycd/index.html ...
(One would hope that he will follow through soon with a "universal" DVD-A / SACD / DVD-V player or upgrade or possibly even a kit !! I would buy one in a New York minute ... do you take PayPal?)
macgyver said:
Have I got something for you. Im an IC design engineer which has just happend to make a ASRC taht is 32bit accurate. Also, it has SPDIF I/O or even I2S/LJ/RJ I/O Any input format can be converted to output format too. If you want to know more, just let me know. By the way, the ASRC can "eat" 400ns of jitter and clean it up perfectly to the accuratacy of the output clock. (Which can be from a crystal or oscillar or something.
Dustin
What is that part, already in the markets?Guido Tent said:
With blocking jittter I mean having a recording/playback chain that has physically low jitter at any position in the chain. Random jitter at only one position can cover regular jitter no matter of whether it is before or after it.
Of course upsampling of min. factor 2 is essential, otherwise the Nyquist frequency is phase-fixed again.
Hi,
Yes that is the snag, the part is ready to go to mass production, but still not wuite there. I looks at AD1896 ASRC and it seems to be descent. THe biggest advantage to the one I have designed is that it also incorporates a SPDIF input. So what I use it a lot for is take SPDIF (with jitter), then output I2S to a DAC. Another feature is that the upsample raito and down sampling ratio is essentiall from 0kHz : 220kHz and 220kHz to 0kHz. It simplly will just lock on any input rate and give you any output rate. One thing it is limited to is the output sample rate refference clock MUST be 256FS. Looking back at why I did this was just because I thought it would be fine. The next rev of the chip will have 256/384/512/768...
If anyone has any "requests" that they would think are useful in an ASRC, just let me know and I can look at it. For performance.
Its a full 32 bit ASRC, so the typical performance is only limited by the quantization noise of a 24bit input data source. With the 24bit data source, the DNR is -144dB and the THD is -144 dB. There is simple noarticfacts whatsoever. (Yes I was pleasently surprised once I fired up the test samples too).
This chip is a 99% digital chip, meaning that there is only a tiny analog section. THe annalog section is actually just a internal clock that I have used to run the FIR filters. Another cool feature which I not usre all ASRC chips have is the ability to relock to he input data stream without any need for a reset to be pushed. I know some of the cystal parts do require this from time to time.
Well if someone is really intereseted I may be able to send some engineering samples, I just dont have tons of them though.
Let me know.
Thanks
Dustin
Yes that is the snag, the part is ready to go to mass production, but still not wuite there. I looks at AD1896 ASRC and it seems to be descent. THe biggest advantage to the one I have designed is that it also incorporates a SPDIF input. So what I use it a lot for is take SPDIF (with jitter), then output I2S to a DAC. Another feature is that the upsample raito and down sampling ratio is essentiall from 0kHz : 220kHz and 220kHz to 0kHz. It simplly will just lock on any input rate and give you any output rate. One thing it is limited to is the output sample rate refference clock MUST be 256FS. Looking back at why I did this was just because I thought it would be fine. The next rev of the chip will have 256/384/512/768...
If anyone has any "requests" that they would think are useful in an ASRC, just let me know and I can look at it. For performance.
Its a full 32 bit ASRC, so the typical performance is only limited by the quantization noise of a 24bit input data source. With the 24bit data source, the DNR is -144dB and the THD is -144 dB. There is simple noarticfacts whatsoever. (Yes I was pleasently surprised once I fired up the test samples too).
This chip is a 99% digital chip, meaning that there is only a tiny analog section. THe annalog section is actually just a internal clock that I have used to run the FIR filters. Another cool feature which I not usre all ASRC chips have is the ability to relock to he input data stream without any need for a reset to be pushed. I know some of the cystal parts do require this from time to time.
Well if someone is really intereseted I may be able to send some engineering samples, I just dont have tons of them though.
Let me know.
Thanks
Dustin
So far what's bothered me most with common SRC's is that they're all optimised for short latency, resulting in equiripple designs with pretty large end spikes. If you could have nice long windowed sinc filters as an option that would make the chip an instant seller for me. See if you can get the lowest setting of the loop filter bandwith really, really low. When one looks at the cirrus 32 bit ASRC, the FFT's clearly show the clock phase roundoff error as skirts around the test tone. In many systems this error is greater than the jitter we're trying to attenuate. The TI chips (at low jitter levels at least) seem to hold the ratio register for up to 4 seconds, resulting in a pretty clean conversion.
Bruno Putzeys said:
Hi Bruno,
Yes when I was designing the ASRC I ran into the problem that the higher my "PLL" bandwidth, the worse the SRC got. Lowering the loop bandwidth does create a better SRC, however something bad happens. If the bandwidth is too low, and your source sample rate is not rock solid (jitter, or just any slight frequency variation) then the locked output would get tiny glitches in it when the ASRC accidentally missed an input sample point or grabbed one twice. Its like this. Imagine I lock my "PLL" to the input rate at say 44.10000kHz and then lowered the loop bandwidth soo low it could not repspond to the input rate changing to 44.10001kHz before the PLL misses one of the input samples since its only looking for data at 44.10000kHz but the data is now actually coming at 44.10001kHz. This was the hardest part of the ASRC design was haveing enough loop bandwidth to handle source data rate variation, but not too much that it causes errors in the SRC.
CLD
Which window? Blackman-Harris..Hann..?
Also, It can be done very easily. (just change the coefficients of the FIR filters) Perhaps I can add a couple ROM's with various filters. 1 for best image rejection, and other for the windowed sinc option..... I will look more into this for sure. Guess the question is, how much image rejection would you be willing to live with at the expense of a windowed sinc filter?
CLD
Also, It can be done very easily. (just change the coefficients of the FIR filters) Perhaps I can add a couple ROM's with various filters. 1 for best image rejection, and other for the windowed sinc option..... I will look more into this for sure. Guess the question is, how much image rejection would you be willing to live with at the expense of a windowed sinc filter?
CLD
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