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Old 3rd November 2006, 04:21 PM   #11
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Hi,

Yes that is the snag, the part is ready to go to mass production, but still not wuite there. I looks at AD1896 ASRC and it seems to be descent. THe biggest advantage to the one I have designed is that it also incorporates a SPDIF input. So what I use it a lot for is take SPDIF (with jitter), then output I2S to a DAC. Another feature is that the upsample raito and down sampling ratio is essentiall from 0kHz : 220kHz and 220kHz to 0kHz. It simplly will just lock on any input rate and give you any output rate. One thing it is limited to is the output sample rate refference clock MUST be 256FS. Looking back at why I did this was just because I thought it would be fine. The next rev of the chip will have 256/384/512/768...

If anyone has any "requests" that they would think are useful in an ASRC, just let me know and I can look at it. For performance.

Its a full 32 bit ASRC, so the typical performance is only limited by the quantization noise of a 24bit input data source. With the 24bit data source, the DNR is -144dB and the THD is -144 dB. There is simple noarticfacts whatsoever. (Yes I was pleasently surprised once I fired up the test samples too).


This chip is a 99% digital chip, meaning that there is only a tiny analog section. THe annalog section is actually just a internal clock that I have used to run the FIR filters. Another cool feature which I not usre all ASRC chips have is the ability to relock to he input data stream without any need for a reset to be pushed. I know some of the cystal parts do require this from time to time.

Well if someone is really intereseted I may be able to send some engineering samples, I just dont have tons of them though.


Let me know.

Thanks

Dustin
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Old 3rd November 2006, 04:35 PM   #12
Nixie is offline Nixie  Canada
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Quote:
Originally posted by dusfor99
the part is ready to go to mass production, but still not wuite there.
Well, which is it? It's either ready for production which is the same as it being quite there, or not quite there which is the same as not ready for production. You can't have it both ways.

Quote:
Well if someone is really intereseted I may be able to send some engineering samples, I just dont have tons of them though.
I'd be more interested in a preliminary datasheet.
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Old 3rd November 2006, 05:50 PM   #13
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So far what's bothered me most with common SRC's is that they're all optimised for short latency, resulting in equiripple designs with pretty large end spikes. If you could have nice long windowed sinc filters as an option that would make the chip an instant seller for me. See if you can get the lowest setting of the loop filter bandwith really, really low. When one looks at the cirrus 32 bit ASRC, the FFT's clearly show the clock phase roundoff error as skirts around the test tone. In many systems this error is greater than the jitter we're trying to attenuate. The TI chips (at low jitter levels at least) seem to hold the ratio register for up to 4 seconds, resulting in a pretty clean conversion.
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Old 4th November 2006, 02:38 AM   #14
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Quote:
Originally posted by Nixie

Well, which is it? It's either ready for production which is the same as it being quite there, or not quite there which is the same as not ready for production. You can't have it both ways.


I'd be more interested in a preliminary datasheet.

Ok well the status of the chip is that the engineering samples have come back working 100%. The next step is to generate the masks for MP now. This is realisitcally 1-2 months away.

I have attached a couple plots showing the ASRC performance


CLD
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File Type: zip fft_results.zip (66.6 KB, 158 views)
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Old 4th November 2006, 03:21 AM   #15
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Quote:
Originally posted by Bruno Putzeys
So far what's bothered me most with common SRC's is that they're all optimised for short latency, resulting in equiripple designs with pretty large end spikes. If you could have nice long windowed sinc filters as an option that would make the chip an instant seller for me. See if you can get the lowest setting of the loop filter bandwith really, really low. When one looks at the cirrus 32 bit ASRC, the FFT's clearly show the clock phase roundoff error as skirts around the test tone. In many systems this error is greater than the jitter we're trying to attenuate. The TI chips (at low jitter levels at least) seem to hold the ratio register for up to 4 seconds, resulting in a pretty clean conversion.

Hi Bruno,

Yes when I was designing the ASRC I ran into the problem that the higher my "PLL" bandwidth, the worse the SRC got. Lowering the loop bandwidth does create a better SRC, however something bad happens. If the bandwidth is too low, and your source sample rate is not rock solid (jitter, or just any slight frequency variation) then the locked output would get tiny glitches in it when the ASRC accidentally missed an input sample point or grabbed one twice. Its like this. Imagine I lock my "PLL" to the input rate at say 44.10000kHz and then lowered the loop bandwidth soo low it could not repspond to the input rate changing to 44.10001kHz before the PLL misses one of the input samples since its only looking for data at 44.10000kHz but the data is now actually coming at 44.10001kHz. This was the hardest part of the ASRC design was haveing enough loop bandwidth to handle source data rate variation, but not too much that it causes errors in the SRC.


CLD
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Old 4th November 2006, 03:40 AM   #16
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Quote:
Originally posted by dusfor99


Its a full 32 bit ASRC, so the typical performance is only limited by the quantization noise of a 24bit input data source. With the 24bit data source, the DNR is -144dB and the THD is -144 dB. There is simple noarticfacts whatsoever. (Yes I was pleasently surprised once I fired up the test samples too).



Nice. Hope its not for Gennum.
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Old 4th November 2006, 03:42 AM   #17
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Quote:
Originally posted by rfbrw



Nice. Hope its not for Gennum.

Why do you say that? (Its not BTW)


CLD
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Old 4th November 2006, 03:43 AM   #18
Nixie is offline Nixie  Canada
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Quote:
Originally posted by Bruno Putzeys
If you could have nice long windowed sinc filters as an option that would make the chip an instant seller for me.
Seconded!
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Old 4th November 2006, 04:04 AM   #19
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Which window? Blackman-Harris..Hann..?

Also, It can be done very easily. (just change the coefficients of the FIR filters) Perhaps I can add a couple ROM's with various filters. 1 for best image rejection, and other for the windowed sinc option..... I will look more into this for sure. Guess the question is, how much image rejection would you be willing to live with at the expense of a windowed sinc filter?



CLD
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Old 4th November 2006, 04:37 AM   #20
Nixie is offline Nixie  Canada
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I'd say Lanczos. In my experience with image resampling for resizing, it gives the best results. So I figure may be interesting in audio as well. Or a good non-windowed-sinc filter such as a Kaiser-Bessel, allowing one to test different values for its parameter.
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